Title:
LOW-TEMPERATURE POLYCRYSTALLINE SILICON THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
WIPO Patent Application WO/2020/042383
Kind Code:
A1
Abstract:
On a polycrystalline silicon layer (203) are formed, in sequence, a gate insulating layer (204) and an inter-insulating layer (206) and a via pattern thereon; the via pattern comprises a gate trench (211) and source/drain electrode hole (207); by means of using stacked preparation of the gate insulating layer (204) and inter-insulating layer (206), the conditions for the formation of the gate trench (211) are provided; the stacked preparation of the gate insulating layer (204) and inter-insulating layer (206), in conjunction with steps such as vias being fabricated on the gate insulating layer (204) and the inter-insulating layer (206) so as to form a via pattern, and such as the via pattern being filled to fabricate a gate line (205), enables the formation of the gate line (205) and the formation of the via pattern using a same photomask; thus the number of photomasks used is decreased and production costs are reduced.
Inventors:
CHEN CHEN (CN)
Application Number:
PCT/CN2018/116302
Publication Date:
March 05, 2020
Filing Date:
November 20, 2018
Export Citation:
Assignee:
WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD (CN)
International Classes:
H01L21/84; H01L27/12
Foreign References:
| CN106847744A | 2017-06-13 | |||
| CN106847744A | 2017-06-13 | |||
| CN104637955A | 2015-05-20 | |||
| CN107946368A | 2018-04-20 | |||
| CN105097550A | 2015-11-25 |
Attorney, Agent or Firm:
ESSEN PATENT&TRADEMARK AGENCY (CN)
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