1. An RF MOSFET, comprising respective pluralities of gate fingers, source fingers, and drain fingers formed on a semiconductor structure, the gate fingers being spaced apart from each other along a first direction, extending in a second, orthogonal direction, and electrically connected to one another through a gate mandrel that is electrically connected to a gate contact, the source fingers being spaced apart from each other along the first direction, extending in the second direction, and electrically connected to one another through a source mandrel that is electrically connected to respective source contacts, and the drain fingers being spaced apart from each other along the first direction, extending in the second direction, and electrically connected to one another through a drain mandrel that is electrically connected to respective drain contacts, the respective source, gate, and drain fingers further being interdigitated so that each gate finger extends in the first direction between a pair of adjacent source and drain fingers, the RF MOSFET electrically organized as a plurality of unit cell transistors electrically connected with one another and adjacent unit cell transistors of the RF MOSFET being separated from one another by a dummy gate and trench that extends into the semiconductor structure, wherein the semiconductor structure includes a buried stressor layer.

2. The RF MOSFET of claim 1, wherein the semiconductor structure is a bulk semiconductor substrate with the buried stressor layer disposed over the semiconductor substrate and a semiconductor layer disposed over the buried stressor layer.

3. The RF MOSFET of claim 1, wherein the semiconductor structure is a PD-SOI wafer including a semiconductor substrate, a BOX layer disposed over the semiconductor substrate, a semiconductor layer disposed over the BOX layer, the buried stressor layer disposed over the semiconductor layer, and a partially depleted semiconductor layer disposed over the buried stressor layer.

4. The RF MOSFET of claim 1, wherein the semiconductor structure is an FD-SOI wafer including a semiconductor substrate, the buried stressor layer disposed over the

AMENDED SHEET (ARTICLE 19) semiconductor substrate, a BOX layer disposed over buried stressor layer, and a fully depleted semiconductor layer disposed over the BOX layer.

5. The RF MOSFET of claim 1, wherein the dummy gates are not electrically connected to the gate mandrel.

6. The RF MOSFET of claim 1, wherein the gate, source and drain fingers are each made of a conductive material.

7. The RF MOSFET of claim 1, wherein each unit cell transistor includes one of the gate fingers, one of the source fingers, and one of the drain fingers, the included source and drain fingers being on opposed sides of the included gate finger, and a portion of the semiconductor structure that underlies the included gate, source and drain fingers.

8. The RF MOSFET of claim 1, wherein the source fingers and drain fingers comprise elevated epitaxial silicon source/drain regions and a source/drain of each unit cell transistor is located inside the included portion of the semiconductor structure that underlies an adjacent a channel region below a respective included gate finger.

9. The RF MOSFET of claim 1, wherein the buried stressor layer comprises SiGe.

10. The RF MOSFET of claim 2, wherein the trenches extend through the semiconductor layer and the buried stressor layer and into the underlying substrate.

11. The RF MOSFET of claim 3, wherein the trenches extend through the partially depleted semiconductor layer, the buried stressor layer, the semiconductor layer, and into the BOX layer.

12. The RF MOSFET of claim 3, wherein the trenches extend through the partially depleted semiconductor layer, the buried stressor layer, the semiconductor layer, the BOX layer and partially into the substrate.

13. The RF MOSFET of claim 4, wherein the trenches extend through the fully depleted semiconductor layer, the BOX layer, the buried stressor layer, and into the substrate.

AMENDED SHEET (ARTICLE 19)