Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MASK AND LAYOUT METHOD THEREFOR, AND TYPESETTING PATTERN OF CHIP
Document Type and Number:
WIPO Patent Application WO/2024/066218
Kind Code:
A1
Abstract:
A mask and a layout method therefor, and a typesetting pattern (500) of a chip. The mask comprises: a chip pattern region, which comprises a plurality of chip pattern groups (501) distributed at intervals in a first direction (a), wherein each chip pattern group (501) comprises a plurality of chip patterns (1) distributed at intervals in a second direction (b), the first direction (a) intersecting with the second direction (b); each chip pattern (1) is provided with a cutting region (2) at the periphery, in which cutting region (2) a marking pattern is formed; a test pattern region (3) is between the cutting region (2) and a chip pattern (1) adjacent thereto, and a test pattern is formed in the test pattern region (3); and the width of the portion in the test pattern region (3) that extends in the second direction (b) is less than the width of the portion thereof that extends in the first direction (a), or the width of the portion in the test pattern region (3) that extends in the first direction (a) is less than the width of the portion thereof that extends in the second direction (b).

Inventors:
JIN ZHI (CN)
Application Number:
PCT/CN2023/080919
Publication Date:
April 04, 2024
Filing Date:
March 10, 2023
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G03F1/70; G03F1/42; G03F1/44
Foreign References:
JP2006030466A2006-02-02
CN105336685A2016-02-17
CN113921500A2022-01-11
CN113433791A2021-09-24
CN102339816A2012-02-01
US20090068772A12009-03-12
US20210305287A12021-09-30
Attorney, Agent or Firm:
BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)
Download PDF: