MATRIX CONTROLLER

WIPO Patent Application WO/1990/008998

A1

A matrix controller for recognizing the conditions of a plurality of switches. The switches are arranged at the intersecting points 1F (ME11 to ME44) of a matrix, two per point, and are provided with sets of diodes for preventing the run-around. Each of the sets comprises four diodes, with the two diodes opposite to the others. There are provided with first drivers (CDV1 to CDV4) for driving columns (COL1 to COL4) of the matrix at the high or low level, second drivers (RDV1 to RDV4) for driving rows (ROW1 to ROW4) of the matrix at the high or low level, and receivers (RV1 to RV4) which are connected to the rows of the matrix to recognize the conditions. Each of the columns (COL1 to COL4) of the matrix comprises two lines, each connected to a couple of the diodes, for example, one line of the column (COL1) connected to the diodes (D1a1 and D1a2) and the other connected to the diodes (D1b1 and D1b2). The two couples in each column are parallel but opposite in polarity. The tail of one couple of the diodes and the head of the other in each column are connected to the corresponding first driver through a line. For recognition of the conditions, the levels of the first drivers (CDV1 to CDV4) and the second drivers (RDV1 to RDV4) are made reverse to each other. Thus, the number of switches whose conditions are recognized are twice that of conventional techniques with the same number of the interface lines. Further, the recognition of and the dynamic display by LEDs are effected through the same matrix. Switching of the LEDs is controlled excepting the time when the conditions are recognized.

YONEKURA MIKIO (JP)

PCT/JP1990/000051

August 09, 1990

January 17, 1990

Click for automatic bibliography generation  

FANUC LTD (JP)

G06F3/02; G06F3/023; H03M11/20; (IPC1-7): G06F3/023

JPS62209609A	1987-09-14
JPS62173514A	1987-07-30
JPS61107418A	1986-05-26

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