Title:
MEMORY ACCESS DEVICE, MEMORY SYSTEM, AND INFORMATION PROCESSING SYSTEM
Document Type and Number:
WIPO Patent Application WO/2019/077812
Kind Code:
A1
Abstract:
The objective of the present invention is to cause memory devices which have different data sizes and access speeds and which are accessed in parallel to operate efficiently as cache memory. This memory access device accesses first and second memory devices which have different data sizes and access speeds, are accessed in parallel, and each include a plurality of memories that can be accessed in parallel. The memory access device is provided with a management information storage unit and an access control unit. The management information storage unit associates and stores, as management information, respective management units corresponding to the first and second memory devices. The access control unit accesses one of the first and second memory devices on the basis of the management information.
Inventors:
OKUBO HIDEAKI (JP)
NAKANISHI KENICHI (JP)
KANEDA TERUYA (JP)
NAKANISHI KENICHI (JP)
KANEDA TERUYA (JP)
Application Number:
PCT/JP2018/025468
Publication Date:
April 25, 2019
Filing Date:
July 05, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G06F12/0868; G06F12/0871; G06F12/0873
Foreign References:
| JP2007041904A | 2007-02-15 | |||
| JP2009266125A | 2009-11-12 | |||
| JPH10154101A | 1998-06-09 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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