Title:
MEMORY CELL AND MEMORY CELL ARRAY
Document Type and Number:
WIPO Patent Application WO/2021/176908
Kind Code:
A1
Abstract:
A memory cell array according to the present disclosure comprises a plurality of memory cells 11 arrayed in a first direction and a second direction different from the first direction, wherein each of the memory cells 11 is composed of a resistance-variable nonvolatile memory element and a selecting transistor TR electrically connected to the nonvolatile memory element. The selecting transistor TR is formed in an active region 80 provided in a semiconductor layer 60. At least a part of the active region 80 is in contact with an element-isolating region 81 provided in the semiconductor layer 60. The surface of the element-isolating region 81 is positioned lower than the surface of the active region 80.
Inventors:
OKA MIKIO (JP)
YAMAGUCHI KAZUKI (JP)
KINO MASASHI (JP)
DOI TAKASHIGE (JP)
MORITOKI MASASHIGE (JP)
WATANABE TAKASHI (JP)
KASAHARA NORIKAZU (JP)
YAMAGUCHI KAZUKI (JP)
KINO MASASHI (JP)
DOI TAKASHIGE (JP)
MORITOKI MASASHIGE (JP)
WATANABE TAKASHI (JP)
KASAHARA NORIKAZU (JP)
Application Number:
PCT/JP2021/003243
Publication Date:
September 10, 2021
Filing Date:
January 29, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L49/00; H01L21/8239; H01L27/105; H01L29/82; H01L43/08
Foreign References:
| JP2007149800A | 2007-06-14 | |||
| JP2010239147A | 2010-10-21 | |||
| JP2013042140A | 2013-02-28 | |||
| JP2007273493A | 2007-10-18 |
Attorney, Agent or Firm:
SAKAI INTERNATIONAL PATENT OFFICE (JP)
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