MEMORY CELL STRUCTURE, MEMORY MANUFACTURING METHOD, AND MEMORY DEVICE

WIPO Patent Application WO/2015/060144

A1

The present disclosure relates to a memory cell structure enabling the provision of a memory cell structure of an MRAM, which achieves a reduction in the resistance of lead-out lines connected to an MTJ, a reduction in the area of a memory cell, and the avoidance of the deterioration of the performance of the MTJ due to heat, and also relates to a memory manufacturing method and a memory device. A memory cell is provided with: a transistor in which a first diffusion layer formed at the bottom of a recess formed by working a silicon substrate into a groove shape, and a second diffusion layer formed at the respective upper ends of two opposite sidewall portions of the recess are used, and a channel is formed in a section between the first diffusion layer and the second diffusion layer in each of the two sidewall portions; and a memory element which is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

JPH0997496	FERROELECTRIC SUBSTANCE MEMORY DEVICE AND DATA READING METHOD
JP5568845	Manufacturing method of semiconductor device
JPS6216561	SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

UMEBAYASHI TAKU (JP)
SUKEGAWA SHUNICHI (JP)
YOKOYAMA TAKASHI (JP)
HOSOMI MASANORI (JP)
HIGO YUTAKA (JP)

PCT/JP2014/077172

April 30, 2015

October 10, 2014

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SONY CORP (JP)

H01L21/8246; H01L21/8242; H01L27/105; H01L27/108; H01L29/82; H01L43/08

JP2010171166A	2010-08-05
JP2012238642A	2012-12-06
JPS63287054A	1988-11-24
JP2013161827A	2013-08-19

NISHIKAWA Takashi et al. (JP)
Nishikawa 孝 (JP)

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