Title:
MEMORY CONTROL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/189045
Kind Code:
A1
Abstract:
The purpose of the present invention is to reduce the withstand voltage for a gate voltage and maximum amplitude in a circuit that selects a memory cell and applies a prescribed voltage to both ends thereof. The memory control circuit comprises a multi-stage memory decoder for selecting a specific cell in a memory in accordance with a specified address and applying a prescribed voltage to both ends thereof. At least one stage in the multi-stage memory decoder comprises four transistors. The first and second transistors are each provided in accordance with a value written to a specific cell. The third and fourth transistors are provided for putting a specific cell into a non-selected state.
Inventors:
TERADA HARUHIKO (JP)
SHIBAHARA YOSHIYUKI (JP)
MORI YOTARO (JP)
SHIBAHARA YOSHIYUKI (JP)
MORI YOTARO (JP)
Application Number:
PCT/JP2020/003476
Publication Date:
September 24, 2020
Filing Date:
January 30, 2020
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G11C13/00
Domestic Patent References:
| WO2016174979A1 | 2016-11-03 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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