Title:
MEMORY CONTROLLER AND FLASH MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2023/100212
Kind Code:
A1
Abstract:
A memory controller according to an embodiment of the present invention is provided with a microprocessor that executes each of a data access process and an update process that updates area management information in accordance with the access process. The microprocessor determines the virtual addresses to be accessed on the basis of area management information that defines a correspondence between logical addresses of logical pages and virtual addresses of virtual pages included in a virtual block that comprises a plurality of physical blocks. When executing data writing processes as access processes on the basis of the determined virtual addresses, the microprocessor edits the area management information in a cache area each time the microprocessor executes a writing process, and writes and saves the edited area management information in a flash memory at a frequency lower than the frequency at which each writing process is executed, thus executing a process for updating the area management information.
Inventors:
TAKUBO KENICHI (JP)
Application Number:
PCT/JP2021/043727
Publication Date:
June 08, 2023
Filing Date:
November 30, 2021
Export Citation:
Assignee:
TDK CORP (JP)
International Classes:
G06F12/02; G06F12/00
Foreign References:
| JP2007249469A | 2007-09-27 | |||
| JP2008243156A | 2008-10-09 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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