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Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2022/219696
Kind Code:
A1
Abstract:
This memory device comprises, on a substrate, a plurality of semiconductor matrix memory cells standing vertically or extending horizontally in relation to the substrate, and performs: a memory write operation in which voltage applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell is controlled to retain a hole group formed by impact ionization or a gate-induced drain leakage current inside a channel semiconductor layer; and a memory delete operation in which voltage applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region is controlled to delete the hole group from inside the channel semiconductor layer. The first impurity layer connects to a source line, the second impurity layer connects to a bit line, and if one of the first gate conductor layer and the second gate conductor layer connects to a word line, the other connects to a first drive control line. After the word line has gone from a first voltage to a second voltage higher than the first voltage, the voltage of the bit line goes from a third voltage to a fourth voltage higher than the third voltage, and a memory read operation is performed in which multiple pieces of data selected by the word line and stored in the semiconductor matrix are read to the bit line.

Inventors:
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2021/015248
Publication Date:
October 20, 2022
Filing Date:
April 13, 2021
Export Citation:
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Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
G11C16/04; G11C11/401; H01L21/8242; H01L27/10; H01L27/108
Foreign References:
JP2008218556A2008-09-18
JP2006080280A2006-03-23
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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