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Patent Searching and Data


Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2022/269740
Kind Code:
A1
Abstract:
This memory device comprises a page constituted by a plurality of memory cells arranged in columns on a substrate, said memory device performing: a page write operation for controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell included in the page, and holding a hole group formed by an impact ionization phenomenon inside a channel semiconductor layer; and a page erase operation for controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, a third gate conductor layer, a fourth gate conductor layer, the first impurity region, and the second impurity region, and removing the hole group from the inside of the channel semiconductor layer. A first impurity layer of the memory cell is connected to a source line, and a second impurity layer is connected to a bit line. One of the first and second gate conductor layers is connected to a word line, and the other is connected to a drive control line. During a refresh operation, at least one word line is selected, voltages to be applied to the selected word line, the drive control line, the source line, and the bit line are controlled, and the voltage for the selected word line in the channel semiconductor layer is reset to the voltage in the page write state by formation of the hole group by the impact ionization phenomenon, inside the channel semiconductor layer.

Inventors:
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2021/023532
Publication Date:
December 29, 2022
Filing Date:
June 22, 2021
Export Citation:
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Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
G11C7/04; G11C16/04; G11C11/401; H01L27/10
Foreign References:
JP2008218556A2008-09-18
JP2006080280A2006-03-23
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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