Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2023/067748
Kind Code:
A1
Abstract:
A memory device according to the present invention is provided with a page which is composed of a plurality of memory cells that are arranged in columns on a substrate. This memory device performs: a page write operation for holding a hole group, which is formed by an impact ionization phenomenon, inside a channel semiconductor layer by controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, a first impurity region and a second impurity region of each of the memory cells contained in the page; and a page erase operation for removing the hole group from the inside of the channel semiconductor layer by controlling the above-described voltages. The first impurity region is connected to a source line; the second impurity region is connected to a bit line; the first gate conductor layer is connected to a first plate line; the second gate conductor layer is connected to a second plate line; and the third gate conductor layer is connected to a word line. The page erase operation is performed without inputting a positive/negative bias pulse to the bit line and the source line.
Inventors:
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2021/038886
Publication Date:
April 27, 2023
Filing Date:
October 21, 2021
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
G11C16/04; G11C11/401; H01L27/10
Foreign References:
| JP2008218556A | 2008-09-18 | |||
| JP2006080280A | 2006-03-23 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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