Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2023/281728
Kind Code:
A1
Abstract:
A dynamic flash memory is formed by stacking, on a P-layer substrate 20, a first dynamic flash memory cell and a second dynamic flash memory cell, wherein the first dynamic flash memory cell is formed as a first Si pillar 22a comprising an N+ layer 21a, a P-layer 22a, and an N+ layer 21b and the second dynamic flash memory cell is formed as a second Si pillar 22b comprising a P-layer 22b and an N+ layer 21c, and shares the use of the N+ layer 21b, which is connected to a first bit line BL1, with the first dynamic flash memory cell. As seen in a plan view, a first plate line PL1, a first word line WL1, a second word line WL2, and a second plate line PL2 are formed to extend in the same direction, and the direction in which the first plate line PL1, the first word line WL1, the second word line WL2, and the second plate line PL2 extend is orthogonal to the direction in which the first bit line BL1 extends.
Inventors:
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
SAKUI KOJI (JP)
Application Number:
PCT/JP2021/025899
Publication Date:
January 12, 2023
Filing Date:
July 09, 2021
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
International Classes:
G11C16/04; G11C11/401; H01L27/10
Foreign References:
| JP2008218556A | 2008-09-18 | |||
| JP2006080280A | 2006-03-23 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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