Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2024/062539
Kind Code:
A1
Abstract:
This memory device, in which in a plan view on a substrate, a page is formed by a plurality of memory cells arranged in the row direction and a plurality of the pages are arranged in the column direction, is characterized in that: the memory cells included in each page have a semiconductor matrix, a first impurity layer on both ends of the semiconductor matrix, a second impurity layer, a first gate conductor layer, a second gate conductor layer, and a channel semiconductor layer; the first impurity layer of the memory cell connects to a source line, the second impurity layer connects to a bit line, one among the first gate conductor layer and the second gate conductor layer connects to a word line, and the other connects to a plate line; a voltage applied across the source line, bit line, word line, and plate line is controlled to perform a page erase operation, a page write operation, and a page read operation; and a first operation in which data of a first page is output to an input/output circuit via a sense amplifier circuit, and a second operation in which data of a second page on the same bank as the first page is read out by the bit line, are performed in parallel.
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Inventors:
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2022/035018
Publication Date:
March 28, 2024
Filing Date:
September 20, 2022
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
G11C16/04; G11C7/08; G11C11/401; H10B12/00; H10B99/00
Domestic Patent References:
| WO2022172318A1 | 2022-08-18 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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