Title:
MEMORY EFFICIENT LDPC DECODING METHODS AND APPARATUS
Document Type and Number:
WIPO Patent Application WO2006017555
Kind Code:
A3
Abstract:
Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state (310) for check node processing operations. The state for a check node (321) is fully updated and then subject to an extraction process (316) to generate check node to variable node messages. The signs of messages received from valiable nodes may be stored by the check node processor module (312) of the invention for use in message extraction. The check node processor (308) can process messages in variable node order (304) thereby allowing the valiable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described.
Inventors:
RICHARDSON TOM (US)
NOVICHKOV VLADIMIR (US)
NOVICHKOV VLADIMIR (US)
Application Number:
PCT/US2005/027526
Publication Date:
November 09, 2006
Filing Date:
August 01, 2005
Export Citation:
Assignee:
FLARION TECHNOLOGIES INC (US)
RICHARDSON TOM (US)
NOVICHKOV VLADIMIR (US)
RICHARDSON TOM (US)
NOVICHKOV VLADIMIR (US)
International Classes:
H03M13/03; H03M13/00
Foreign References:
| US6539367B1 | 2003-03-25 | |||
| US6751770B2 | 2004-06-15 |
Other References:
See also references of EP 1782541A4
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