Title:
MEMORY MODULE AND AUXILIARY MODULE FOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2010/001622
Kind Code:
A1
Abstract:
In a memory module, even if the bit count of a bank address, the bit count of a row address, and the bit count of a column address that are output from a memory controller do not respectively match the bit count of a bank address, the bit count of a row address, and the bit count of a column address that are for identifying a memory cell subject to access, all of the memory cells of the memory module are made accessible and the memory module is allowed to operate normally. A memory module (100) comprises an SDRAM (110) and an address-generating circuit (120). Using the highest ranking bit of a row address output from a memory controller (12), the address-generating circuit (120) generates a bank address (BA2) for the missing highest ranking bit required for identifying the memory cell subject to access and outputs the generated bank address (BA2) to the SDRAM (110).
Inventors:
YUASA KAORU (JP)
Application Number:
PCT/JP2009/003102
Publication Date:
January 07, 2010
Filing Date:
July 03, 2009
Export Citation:
Assignee:
BUFFALO INC (JP)
YUASA KAORU (JP)
YUASA KAORU (JP)
International Classes:
G06F12/06; G06F12/02
Foreign References:
| JP2001022635A | 2001-01-26 | |||
| JPH05334183A | 1993-12-17 | |||
| JP3635899B2 | 2005-04-06 | |||
| JP3600830B2 | 2004-12-15 | |||
| JP3259696B2 | 2002-02-25 | |||
| JP3540388B2 | 2004-07-07 | |||
| JP2006221651A | 2006-08-24 |
Attorney, Agent or Firm:
TOKKYO GYOMUHOJIN MEISEI INTERNATIONAL PATENT FIRM (JP)
Patent business corporation Akinari international patent firm (JP)
Patent business corporation Akinari international patent firm (JP)
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