Title:
MEMORY AND READ CIRCUIT THEREOF
Document Type and Number:
WIPO Patent Application WO/2023/124096
Kind Code:
A1
Abstract:
A memory and a read circuit thereof. The memory comprises a plurality of storage arrays. Each storage array comprises a first array and a second array symmetrical to the structure of the first array. The read circuit of the memory comprises a plurality of bit read circuits in one-to-one correspondence with the plurality of storage arrays. Each bit read circuit comprises a word line control circuit, a bit line control circuit, and a current comparison circuit. According to the present application, the bit read circuits can offset a sub-threshold leakage current introduced onto a bit line, so as to prevent different storage values read from a same storage bit under different scenarios, thereby improving read accuracy of a variable-resistance memory.
Inventors:
SUN HAIJUN (CN)
FANG WEI (CN)
FANG WEI (CN)
Application Number:
PCT/CN2022/111623
Publication Date:
July 06, 2023
Filing Date:
August 11, 2022
Export Citation:
Assignee:
ZHEJIANG HIKSTOR TECH CO LTD (CN)
International Classes:
G11C13/00
Foreign References:
| CN112599167A | 2021-04-02 | |||
| CN106205681A | 2016-12-07 | |||
| CN113593622A | 2021-11-02 | |||
| CN1734674A | 2006-02-15 | |||
| CN105070735A | 2015-11-18 | |||
| US20210027837A1 | 2021-01-28 |
Attorney, Agent or Firm:
UNITALEN ATTORNEYS AT LAW (CN)
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