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Title:
MEMORY AND MEMORY REPAIR METHOD
Document Type and Number:
WIPO Patent Application WO/2023/116212
Kind Code:
A1
Abstract:
A memory and a memory repair method. The memory comprises a storage region, a failure recording region, and a repair circuit. The storage region is provided with redundant bits; the failure recording region is provided with multi-state bits, and the multi-state bits are used for recording position information of failed bits in the storage region; and the repair circuit is used for repairing the failed bits by means of the redundant bits according to the position information. Since the multi-state bits represent ternary or other bases, compared with a traditional binary system, the multi-state bits can be used for storing more information, so that the repair bits used in repair are fewer than those used in a traditional repair mode, the repair efficiency is higher, and the resource consumption is less; moreover, during the working process of the chip, immediate repair can also be implemented, thereby improving the reliability of the chip.

Inventors:
WEI KAI (CN)
ZHOU YAXING (CN)
HE SHIKUN (CN)
XU XIAOBO (CN)
Application Number:
PCT/CN2022/129169
Publication Date:
June 29, 2023
Filing Date:
November 02, 2022
Export Citation:
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Assignee:
ZHEJIANG HIKSTOR TECH CO LTD (CN)
International Classes:
G11C29/00
Domestic Patent References:
WO2014047225A12014-03-27
Foreign References:
US20130322146A12013-12-05
US20210124659A12021-04-29
US20190164621A12019-05-30
CN107039083A2017-08-11
US20150131361A12015-05-14
US20170133108A12017-05-11
Attorney, Agent or Firm:
UNITALEN ATTORNEYS AT LAW CO., LTD. (CN)
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