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Title:
MEMRISTIVE NEUROMORPHIC CIRCUIT AND METHOD FOR TRAINING THE MEMRISTIVE NEUROMORPHIC CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/010048
Kind Code:
A1
Abstract:
A neural network (10) is implemented as a memristive neuromorphic circuit (100) that includes a neuron circuit (112, 114) and a memristive device (113) connected to the neuron circuit (112, 114). A conductance balanced voltage pair is provided for the memristive device (113), where the conductance balanced voltage pair includes a set voltage for increasing the conductance of the memristive device (113) and a reset voltage for decreasing the conductance of the memristive device (113). Either the set voltage and reset voltage, when applied to the memristive device (113), effects a substantially same magnitude conductance change in the memristive device (113) over a predetermined range of conductance of the memristive device (113). The provided voltage pair is stored as a conductance balanced map. A training voltage based on the conductance balanced map is applied to the memristive device (113) to train the neural network (10).

Inventors:
KATAEVA IRINA (JP)
STRUKOV DMITRI B (US)
MERRIKH-BAYAT FARNOOD (US)
Application Number:
PCT/JP2016/003000
Publication Date:
January 19, 2017
Filing Date:
June 22, 2016
Export Citation:
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Assignee:
DENSO CORP (JP)
UNIV CALIFORNIA (US)
International Classes:
G06N3/063
Foreign References:
US20110004579A12011-01-06
US20120016829A12012-01-19
US20120011090A12012-01-12
US20150178619A12015-06-25
US20150006455A12015-01-01
Other References:
JO, SUNG HYUN ET AL.: "Nanoscale Memristor Device as Synapse in Neuromorphic Systems", NANO LETT, vol. 10, no. 4, 1 March 2010 (2010-03-01), pages 1297 - 1301, XP055200946
CANTLEY, KURTIS D. ET AL.: "Hebbian Learning in Spiking Neural Networks With Nanocrystalline Silicon TFTs and Memristive Synapses", IEEE TRANSACTIONS ON NANOTECH, vol. 10, no. 5, 13 January 2011 (2011-01-13), pages 1066 - 1073, XP011359218
Attorney, Agent or Firm:
KIN, Junhi (JP)
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