RELATED PATENT APPLICATION

This application claims priority to commonly owned United States Provisional Patent Application No. 63/312,917 filed February 23, 2022, the entire contents of which are hereby incorporated by reference for all purposes.

TECHNICAL FIELD

The present disclosure relates to integrated circuit components, and more particularly to metal-insulator-metal (MIM) capacitors formed in integrated circuits.

BACKGROUND

A metal-insulator-metal (MIM) capacitor is a capacitor constructed with a metal top electrode, a metal bottom electrode, and an insulator (dielectric) sandwiched between the two electrodes.

MIM capacitors are important components in many electrical circuits, for example many analog, mixed-signal, and radio-frequency complementary metal-oxide semiconductors (RF CMOS) circuits. MIM capacitors typically provide better performance than alternatives, such as POP (poly-oxide-poly) capacitors and MOM (metal-oxide-metal lateral flux) capacitors, due to lower resistance, better matching for analog circuits (e.g., matching device characteristics such as resistance and capacitance), and/or better signal/noise characteristics.

MIM capacitors are typically constructed between two interconnect metal layers (e.g., aluminum layers), referred to as metal layers M _x and M _x +i. For example, an MIM capacitor may be formed using an existing metal layer M _x as the bottom plate (bottom electrode), constructing an insulator and a top plate (top electrode) over the bottom electrode, and connecting an overlying metal layer M _x +i to the top and bottom plates by respective vias. The top plate formed between the two metal layers M _x and M _x +i may be formed from a different metal than the metal layers M _x and M _x +i. For example, the metal layers M _x and M _x +i may be formed from aluminum, whereas the top plate may be formed from titanium/titanium nitride (Ti/TiN), tantalum/tantalum nitride (Ta/TaN), or tungsten (W), for example.

The top electrode typically has a higher resistance than the bottom electrode, for example because the top electrode may be limited by thickness constraints and the material of choice, thus limiting the performance of conventional MIM capacitors. MIM capacitors typically have very narrow process margins, particularly for a metal etch used to form the top electrode.

Conventional MIM capacitors are also typically expensive to build. For example, MIM capacitors typically require multiple additional mask layers and many additional process steps.

In addition, for MIM capacitors formed in aluminum interconnect (i.e., where metal layers M _x and M _x +i comprise aluminum interconnect layers), the aluminum bottom electrode may be susceptible to hillock formation at a top side of the bottom electrode, e.g., resulting from high-temperature processing of aluminum, a low-melting-point metal. Hillocks formed on the bottom electrode may negatively or unpredictably affect the breakdown voltage of the MIM capacitor.

There is a need for MIM capacitors that can be manufactured at lower cost, with few or no added mask layers, and/or with improved breakdown voltage.

SUMMARY

A MIM capacitor module includes a bottom electrode including a bottom electrode cup, an insulator cup formed in the bottom electrode cup, and a top electrode formed in the insulator cup. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the bottom electrode cup base. The insulator cup includes a laterally-extending insulator cup base formed over the bottom electrode cup base, and an insulator cup sidewall extending upwardly from the insulator cup base. The MIM capacitor module includes a dielectric sidewall spacer laterally between the insulator cup sidewall and bottom electrode cup sidewall. The dielectric sidewall spacer reduces a capacitive coupling between the top electrode and the bottom electrode cup sidewall (e.g., in a lateral direction). As a result, the MIM capacitor module effectively functions as a planar capacitor, defined by a capacitive coupling between the top electrode and the laterally- extending bottom electrode cup base, through the laterally-extending insulator cup base. The present MIM capacitor module may thus provide certain characteristics and/or advantageous associated with planar capacitors, e.g., as compared with “3D” MIM capacitors that utilize capacitive coupling between a top electrode and both a lateral base and a vertical sidewall of a cup-shaped bottom electrode. For example, the present MIM capacitor module may provide better matching for analog circuits (e.g., matching device characteristics such as resistance and capacitance), and/or higher breakdown voltage without suffering from an enhanced electric field at the corners. As used herein, a “MIM capacitor module” includes the fundamental elements of an MIM capacitor, e.g., an insulator (dielectric) arranged between conductive electrodes (e.g., conductive plates), and may also include certain related elements, e.g., conductive elements providing electrical contact to the conductive electrodes, and in the examples disclosed herein, a dielectric sidewall spacer.

In addition, the lateral spacing (provided by the dielectric sidewall spacer) of the bottom electrode cup sidewall from the top electrode allows the formation of both a top electrode connection pad (formed on a top surface of the top electrode) and a bottom electrode connection pad (formed on a top surface of the bottom electrode cup sidewall) in a common (i.e., same) metal layer without the need for additional mask layers.

In some examples, the MIM capacitor module may be constructed concurrently with an interconnect structure. In some examples, the MIM capacitor module may be constructed using a damascene process without added photomask layers, as compared with a background IC fabrication process.

In some examples the MIM capacitor module provides a consistent breakdown voltage. For example, disclosed processes for forming the MIM capacitor module may avoid the presence of hillocks on the bottom electrode. In addition, the thickness of the top electrode and overlying top electrode connection pad (which, for example, can both be formed from aluminum) may be large, this providing a very low series resistance.

In some examples, the MIM capacitor module may be constructed between two metal interconnect layers, or between a silicided polysilicon layer and a metal-1 metal layer.

One aspect provides a MIM capacitor module including a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. In some examples, the laterally-extending insulator cup base covers only a partial area of the laterally-extending bottom electrode cup base, due to the presence of the dielectric sidewall spacer.

In some examples, the MIM capacitor module includes (a) a bottom electrode base formed in a lower metal layer, wherein the bottom electrode cup is formed on the bottom electrode base, and (b) a top electrode connection pad formed in an upper metal layer and conductively connected to the top electrode.

In some examples, the lower metal layer and the upper metal layer comprise respective interconnect metal layers. In other examples, the bottom electrode base comprises a metal silicide layer formed on a polysilicon structure.

In some examples, the MIM capacitor module includes a top electrode connection pad and a bottom electrode connection pad formed in an upper metal layer, wherein the top electrode connection pad is conductively connected to the top electrode, and wherein the bottom electrode connection pad is laterally spaced apart from the top electrode connection pad and conductively connected to the bottom electrode cup.

In some examples, the bottom electrode connection pad defines a closed-loop shape that surrounds the top electrode connection pad.

In some examples, the dielectric sidewall spacer comprises silicon oxide, fluorosilicate glass (FSG), organosilicate glass (OSG), or porous OSG.

In some examples, the dielectric sidewall spacer has a lateral thickness in the range of 2000A-5000A.

Another aspect provides an integrated circuit structure including an interconnect structure and a MIM capacitor module. The interconnect structure includes a lower interconnect element formed in a lower metal layer, an upper interconnect element formed in an upper metal layer, and an interconnect via formed in a dielectric region between the lower metal layer and the upper metal layer lower. The MIM capacitor module includes a bottom electrode cup base, a bottom electrode cup, an insulator cup, a dielectric sidewall spacer, and a top electrode. The bottom electrode cup base is formed in the lower metal layer. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. The dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.

In some examples, the integrated circuit structure includes a top electrode connection pad formed in the upper metal layer and conductively connected to the top electrode.

In some examples, the integrated circuit structure includes a bottom electrode connection pad formed in the upper metal layer and spaced apart from the top electrode connection pad, wherein the bottom electrode connection pad is conductively connected to the bottom electrode cup.

In some examples, the lower metal layer and the upper metal layer respectively comprise interconnect metal layers.

In some examples, the lower metal layer comprises a silicided polysilicon layer, wherein the lower interconnect element and the bottom electrode base comprise a respective metal silicide layer formed on a respective polysilicon structure.

Another aspect provides a method, including forming a tub opening in a dielectric region; depositing a conformal metal layer to form a bottom electrode cup in the tub opening, the bottom electrode cup including a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base; depositing a dielectric spacer layer extending into an opening defined by the bottom electrode cup; removing portions of the dielectric spacer layer to define a dielectric sidewall spacer laterally adjacent the bottom electrode cup sidewall; depositing an insulator layer to form an insulator cup, the insulator cup including a laterally-extending insulator cup base over the laterally-extending bottom electrode cup base and an insulator cup sidewall laterally adjacent the dielectric sidewall spacer, wherein the dielectric sidewall spacer is positioned laterally between the insulator cup sidewall and the bottom electrode cup sidewall; depositing a top electrode layer over the insulator layer, the top electrode layer extending into an opening defined by the insulator cup ; and performing a planarization process to partially remove the top electrode layer, wherein a remaining portion of the top electrode layer defines a top electrode.

In some examples, the method includes forming a bottom electrode base in a lower metal layer, forming the dielectric region over the lower metal layer, forming the tub opening over the bottom electrode base, and forming a top electrode connection pad in an upper metal layer, wherein the top electrode connection pad is conductively connected to the top electrode.

In some examples, the method includes forming a bottom electrode connection pad in the upper metal layer, the bottom electrode connection pad spaced apart from the top electrode connection pad and conductively connected to the bottom electrode cup.

In some examples, the lower metal layer and the upper metal layer comprise respective interconnect metal layers. In other examples, the lower metal layer comprises a silicided polysilicon layer, wherein the bottom electrode base comprises a metal silicide layer formed on a polysilicon structure.

In some examples, the method includes forming a lower interconnect element in the lower metal layer, forming an interconnect via opening in the dielectric region, and depositing the conformal metal layer to form (a) the bottom electrode cup in the tub opening and (b) an interconnect via in the interconnect via opening.

In some examples, the deposited dielectric spacer layer defines a cup-shaped dielectric spacer layer structure including (a) a laterally-extending dielectric spacer layer region over the laterally-extending bottom electrode cup base and (b) a dielectric spacer layer sidewall extending upwardly from the laterally-extending dielectric spacer layer region; and selectively removing portions of the dielectric spacer layer comprises performing an anisotropic etch to remove the laterally-extending dielectric spacer layer region over the laterally-extending bottom electrode cup base.

In some examples, performing the planarization process comprises performing a chemical mechanical planarization (CMP) process to remove upper portions of the top electrode layer, insulator layer, dielectric spacer layer and conformal metal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Example aspects of the present disclosure are described below in conjunction with the figures, in which:

Figure 1 A is a top down view and Figure IB is a side cross-sectional view of an example MIM capacitor module;

Figure 2 is a side cross-sectional view showing an example IC structure including a MIM capacitor module and an interconnect structure, which may be formed concurrently, according to one example; Figures 3 A-3 J show an example method of forming the example IC structure shown in Figure 2, including a MIM capacitor module and interconnect structure; and

Figure 4 is a side cross-sectional view showing an example IC structure including an MIM capacitor module and an interconnect structure formed on a lower metal layer comprising a silicided polysilicon layer.

It should be understood the reference number for any illustrated element that appears in multiple different figures has the same meaning across the multiple figures, and the mention or discussion herein of any illustrated element in the context of any particular figure also applies to each other figure, if any, in which that same illustrated element is shown.

DETAILED DESCRIPTION

Figures 1A and IB show an example MIM capacitor module 100 according to the present disclosure. In particular, Figure 1A shows a top view of the MIM capacitor module 100, and Figure IB shows a side cross-sectional view of the MIM capacitor module 100 through cut line 1B-1B shown in Figure 1A. As shown, the MIM capacitor module 100 includes (a) a bottom electrode 102 including a bottom electrode base 104 and a bottom electrode cup 106 formed over the bottom electrode base 104, (b) an insulator cup 108 formed in an opening defined by the bottom electrode cup 106, (c) a top electrode 110 formed in an opening defined by the insulator cup 108, (d) a top electrode connection pad 112 conductively connected to the top electrode 110, and (e) a bottom electrode connection pad 114 conductively connected to the bottom electrode cup 106.

In another example, the bottom electrode base 104 may be omitted; in such example, the bottom electrode cup 106 may be formed on an underlying dielectric region rather than being formed on the bottom electrode base 104 as shown in Figures 1 A and IB. For example, the bottom electrode cup 106 may be formed on an oxide region with the use of a suable etch stop layer to control a depth of a tub opening etch for a tub opening in which the bottom electrode cup 106 may be formed.

The bottom electrode base 104 may be formed in a lower metal layer M _x , for example a lower metal interconnect layer (e.g., an aluminum interconnect layer) or a silicided polysilicon layer, as discussed below in more detail.

The bottom electrode cup 106 may be formed in a dielectric region 116 (e.g., an InterMetal Dielectrics (IMD) region or a Poly-Metal Dielectrics (PMD) region), and includes (a) a laterally-extending bottom electrode cup base 120 and (b) a bottom electrode cup sidewall 122 extending upwardly from the laterally-extending bottom electrode cup base 120. In this example, the bottom electrode cup sidewall 122 extends upwardly from a lateral perimeter edge of the laterally-extending bottom electrode cup base 120. In some examples, the bottom electrode cup 106 is formed from tungsten (W) or other conformal metal. In some examples, the bottom electrode cup 106 is formed over a liner 107, e.g., comprising TiN.

The insulator cup 108 is formed in an opening defined by the bottom electrode cup 106, and includes (a) a laterally-extending insulator cup base 130 formed over at least a portion of the laterally-extending bottom electrode cup base 120 and (b) an insulator cup sidewall 132 extending upwardly from the laterally-extending insulator cup base 130. In this example, the insulator cup sidewall 132 extends upwardly from a lateral perimeter edge of the laterally- extending insulator cup base 130. In some examples, the insulator cup 108 comprises silicon nitride (SiN), e.g., with a thickness in the range of 250-750A. Alternatively, insulator cup 108 may comprise AI2O3, ZrCh, HfCb, ZrSiOx, HfSiOx, HfAlOx, or Ta20s, or other suitable capacitor insulator material.

As shown in Figures 1A-1B, a dielectric sidewall spacer 136 may be formed between the insulator cup sidewall 132 and the bottom electrode cup sidewall 122, to substantially reduce a capacitive coupling between the top electrode 110 and the bottom electrode cup sidewall 122 (in the x-axis direction). In some examples, the dielectric sidewall spacer 136 comprises a silicon oxide, fluorosilicate glass (FSG), organosilicate glass (OSG), porous OSG, or other low-k dielectric (e.g., having a dielectric constant k less than 4.0), and may have a thickness (in the x-direction) in the range of 2000A-5000A. Those skilled in the art will recognize that the above-mentioned thicknesses may be equally applicable in the y-axis, as seen in Figure 1 A.

The top electrode 110 fills an interior opening defined by the insulator cup 108, and may comprise Al, Ti, TiN, W, or a combination thereof, for example a combination of TiN and Al, and may be deposited by a physical vapor deposition (PVD) process, for example.

The top electrode connection pad 112 and bottom electrode connection pad 114 may be formed in an upper metal layer M _x +i, e.g., a metal interconnect layer or a bond bad layer. The top electrode connection pad 112 and bottom electrode connection pad 114 may have any suitable shapes and sizes. For example, the top electrode connection pad 160 and bottom electrode connection pad 162 may respectively have a square or rectangular shape in an x-y plane, e.g., as shown in Figure 1A. In another example (not shown) the top electrode connection pad 112 and bottom electrode connection pad 114 may respectively have a generally circular shape in the x-y plane. As another example, the top electrode connection pad 112 and/or bottom electrode connection pad 114 may respectively be substantially elongated, e.g., running laterally across the wafer in the x-direction and/or the y-direction. In some examples, the top electrode connection pad 112 and/or bottom electrode connection pad 114 may be omitted, and thus may be optional. For example, the bottom electrode connection pad 114 may be omitted, wherein the bottom electrode cup 106 or bottom electrode base 104 may be contacted from below or laterally from the side, instead of from above.

The top electrode 110 is capacitively coupled to the laterally-extending bottom electrode cup base 120 (laterally extending in the x-axis, and in the y-axis direction) through the laterally-extending insulator cup base 130 (laterally extending in the x-axis, and in the y- axis direction). As noted above, the dielectric sidewall spacer 136 substantially reduces a sidewall capacitive coupling between the top electrode 110 and bottom electrode cup sidewall 122. As a result, the structure of the MIM capacitor module 100 effectively defines a planar capacitor between the top electrode 110 and bottom electrode cup base 120 through the insulator cup base 130, generally indicated by the dashed line PC. This planar capacitor defined by the structure of MIM capacitor module 100 may be suitable or advantageous for particular applications, e.g., as compared with a 3D MIM capacitor in which the insulator cup sidewall 132 is formed directly adjacent bottom electrode cup sidewall 122 (i.e., omitting the dielectric sidewall spacer 136), resulting in capacitive coupling through both the insulator cup base 130 and the insulator cup sidewall 132. For example, a planar capacitor defined by the structure of MIM capacitor module 100 may provide better matching for analog circuits (e.g., matching device characteristics such as resistance and capacitance), and/or higher breakdown voltage without suffering from an enhanced electric field in the comers.

In addition, in some examples the dielectric sidewall spacer 136 provides a sufficient lateral spacing between the top electrode 110 and the bottom electrode cup sidewall 122 to allow formation of both the top electrode connection pad 112 (directly contacting a top surface of the top electrode 110) and bottom electrode connection pad 114 (directly contacting a top surface of the bottom electrode cup sidewall 122) in same metal layer M _x +iwithout the need for additional mask layers. In some examples, e.g., as discussed below, the MIM capacitor module 100 is constructed using a damascene process that adds no additional photomask operations to a background integrated circuit fabrication process.

In some examples, both the top electrode 110 and bottom electrodes base 104 are thick, e.g., having a thickness of at least 2500A in the z-direction, thus providing low resistance. In addition, the bottom electrode cup 106 may be formed from tungsten or other conformal refractory metal, and thus free of hillocks, which may provide consistent and high breakdown voltage for the MIM capacitor module 100.

Figure 2 is a side cross-sectional view showing an example IC structure 200 including the MIM capacitor module 100 shown in Figures 1A-1B and an interconnect structure 202 formed concurrently, according to one example. As mentioned above, the MIM capacitor module 100 may be constructed without adding any photomask operations to the background integrated circuit fabrication process (e.g., the background integrated circuit fabrication process for forming the interconnect structure 202 and/or other IC elements).

As discussed above, MIM capacitor module 100 includes bottom electrode 102 including bottom electrode base 104 and bottom electrode cup 106 including bottom electrode cup base 120 and bottom electrode cup sidewall 122, an insulator cup 108 including insulator cup base 130 and insulator cup sidewall 132, dielectric sidewall spacer 136 between bottom electrode cup sidewall 122 and insulator cup sidewall 132, top electrode 110, top electrode connection pad 112, and bottom electrode connection pad 114. As discussed above, the structure of the MIM capacitor module 100 (including the dielectric sidewall spacer 136 between the insulator cup sidewall 132 and bottom electrode cup sidewall 122) effectively defines a planar capacitor between the top electrode 110 and bottom electrode cup base 120 through the insulator cup base 130, generally indicated by the dashed line PC.

As shown in Figure 2, the interconnect structure 202 may include a lower interconnect element 204 formed in a lower metal layer M _x and an upper interconnect element 210 formed in an upper metal layer M _x +i and connected to the lower interconnect element 204 by interconnect vias 206 formed in a via layer V _x , which interconnect vias 206 may be formed by depositing a conformal via material, e.g., tungsten, into respective via openings. In some examples, interconnect vias 206 are formed over liner 107, e.g., comprising TiN. Each of the lower interconnect element 204 and upper interconnect element 210 may comprise a wire or other laterally elongated structure, or a discrete pad (e.g., having a square or substantially square shape from a top view), or any other suitable shape and structure.

As shown, the lower interconnect element 204 and bottom electrode base 104 may be formed in a lower metal layer M _x . The upper interconnect element 210, top electrode connection pad 112, and bottom electrode connection pad 114 may be formed in an upper metal layer M _x +i. The bottom electrode cup 106, insulator cup 108, dielectric sidewall spacer 136, and top electrode 110 may be formed in a via layer V _x between the lower metal layer M _x and upper metal layer M _x +i, e.g., using a damascene process as discussed below with respect to Figures 3A-3H.

As used herein, a “metal layer,” for example in the context of lower metal layer M _x and upper metal layer M _x +i, may comprise any metal or metalized layer or layers, including (a) a metal interconnect layer, e.g., comprising copper, aluminum or other metal deposited by a subtractive patterning process (e.g., deposition, patterning, and etching of a metal layer) or using a damascene process, or (b) a silicided polysilicon layer including a number of poly silicon regions each having a layer or region of metal silicide formed thereon, for example. For example, in some examples the lower metal layer M _x may be a silicided poly silicon layer and the upper metal layer M _x +i may comprise a first metal interconnect layer, often referred to as metal- 1. In such examples, x=0 such that the lower metal layer M _x = Mo and the upper metal layer M _x +i = Mi (i.e., metal-1). Further, as used herein, an “interconnect structure,” e.g., in the context of the interconnect structure 202 discussed below, may include any type or types of metal layers as defined above.

Figures 3 A-3 J show an example method of forming the example IC structure 200 shown in Figure 2, including MIM capacitor module 100 and interconnect structure 202. As noted above, in other examples, the interconnect structure 202 may be optional, such that MIM capacitor module 100 may be formed by the process described below without the elements of interconnect structure 202.

As shown in Figure 3A, the lower interconnect element 204 and the bottom electrode base 104 are formed in the lower metal layer M _x . In this example, the lower metal layer M _x may comprise a metal interconnect layer, wherein the lower interconnect element 204 and bottom electrode base 104 are respectively formed as metal elements (e.g., aluminum elements). In another example, e.g., as shown in Figure 4 discussed below, the lower metal layer M _x may comprise a silicided polysilicon layer, wherein the lower interconnect element 204 and bottom electrode base 104 respectively comprise a silicide region formed on a respective polysilicon structure.

Dielectric region 116 (e.g., an Inter Metal Dielectrics (IMD) region or Poly Metal Dielectrics (PMD) region) is formed over the lower interconnect element 204 and bottom electrode base 104, which lower interconnect element 204 and bottom electrode base 104 were formed in lower metal layer M _x . Dielectric region 116 may include one or more dielectric materials, e.g., silicon oxide, PSG (phosphosilicate glass), or FSG (fluorine doped glass), or a combination thereof.

Via layer openings 300, including interconnect via openings 302 and a tub opening 304, may be patterned (using a photomask) and etched in the dielectric region 116. Via layer openings 300 may be formed using a plasma etch or other suitable etch, followed by a resist strip or other suitable process to remove remaining portions of photoresist material. The etch process to form via layer openings 300 may be a selective etch that stops on lower interconnect element 204 and bottom electrode base 104 (e.g., comprising aluminum or other metal).

Interconnect via openings 302 may be via openings having a width (or diameter or Critical Dimension (CD)) Wvia in both the x-direction and y-direction in the range of 0.1-0.5 pm, for example.

In contrast, tub opening 304 may have a substantially larger width in the x-direction (Wtub_ _x ) and/or y-direction (Wtub^y) than interconnect via openings 302. The shape and dimensions of the tub opening 304 may be selected based on various parameters, e.g., for effective manufacturing of the MIM capacitor module 100 (e.g., effective formation of the bottom electrode cup 106, insulator cup 108, dielectric sidewall spacer 136, and top electrode 110 in the tub opening 304) and/or for desired performance characteristics of the resulting MIM capacitor module 100. In one example, e.g., as shown in Figure 3A, the tub opening 304 may have a square or rectangular shape from the top view. In other examples, tub opening 304 may have a circular or oval shape from the top view.

As noted above, a width of tub opening 304 in the x-direction (Wtub_ _x ), y-direction (Wtub_y), or both the x-direction and y-direction (Wtub_ _x and Wmb y) may be substantially larger than the width Wvia of interconnect via openings 302 in the x-direction, y-direction, or both the x-direction and y-direction. For example, in some examples, width Wtub_ _x and Wmb y of tub opening 304 are respectively at least twice as large as the width Wvia of interconnect via openings 302. In particular examples, width Wtub_x and Wtub_ y of tub opening 304 are respectively at least five time as large or at least 10 times as large as the width Wvia of interconnect via openings 302. In some examples, Wtub_x and Wmb y are respectively in the range of 1-100 pm.

Further, tub opening 304 may be formed with a height-to-width aspect ratio of less than or equal to 1.0 in both the x-direction and y-direction, e.g., to allow effective filling of the tub opening 304 by conformal materials. For example, tub opening 304 may be formed with aspect ratios Htub Vtub_x and Htub/Wtub y respectively in the range of 0.01-1.0, for example in the range of 0.1-1.0. In some examples, aspect ratios Htub/Wtub_x and Htub/Wtub y are respectively less than or equal to 1.0, e.g., for effective filling of tub opening 304 by various materials to form bottom electrode cup 106, insulator cup 108, dielectric sidewall spacer 136, and top electrode 110 in the tub opening 304. For example, tub opening 304 may be formed with aspect ratios Htub/Wtub x and Htub/Wtub y respectively in the range of 0.1-1.0, or more particularly in the range of 0.5-1.0.

Next, as shown in Figure 3B, a liner (or “glue layer”) 107, e.g., comprising TiN with a thickness in the range of 50A-200A, is deposited over the structure and extends into respective via layer openings 300. A conformal metal layer 310 is deposited over the liner 107 and extends into respective via layer openings 300 to (a) fill interconnect via openings 302 to form respective interconnect vias 206, and (b) form the bottom electrode cup 106 in the tub opening 304, wherein the bottom electrode cup 106 includes the laterally-extending bottom electrode cup base 120 and the bottom electrode cup sidewall 122 extending upwardly (in the z-direction) from a lateral perimeter edge of the laterally-extending bottom electrode cup base 120. In one example, the conformal metal layer 310 comprises tungsten deposited with a thickness in the range of 1000A-5000A. In other examples, the conformal metal layer 310 may comprise Co, TiN, or other conformal metal. The conformal metal layer 310 may be deposited by a conformal chemical vapor deposition (CVD) process or other suitable deposition process.

Next, as shown in Figure 3C, a dielectric spacer layer 320 is deposited over the conformal metal layer 310 and extends into an opening 322 defined by the bottom electrode cup 106, to form a cup-shaped dielectric spacer layer structure 324 in the opening 322. The cup-shaped dielectric spacer layer structure 324 includes (a) a laterally-extending dielectric spacer layer base 326 (formed on the laterally-extending bottom electrode cup base 120) and (b) a dielectric spacer layer sidewall 328 (formed adjacent the bottom electrode cup sidewall 122) extending upwardly from the laterally-extending dielectric spacer layer base 326. In some examples, the dielectric spacer layer 320 comprises a silicon oxide, fluorosilicate glass (FSG), organosilicate glass (OSG), porous OSG, or other low-k dielectric (e.g., having a dielectric constant k less than 4.0), deposited with a thickness in the range of 2000A-5000A, i.e., wherein the dielectric spacer layer base 326 has a z-direction thickness in the range of 2000A-5000A and the dielectric spacer layer sidewall 328 has an x-direction thickness, and a y-direction thickness, in the range of 2000A-5000A.

Next, as shown in Figure 3D, portions of the dielectric spacer layer 320 are etched or otherwise removed to define the dielectric sidewall spacer 136 formed laterally adjacent the bottom electrode cup sidewall 122. In one example, an anisotropic (directional) plasma etch without patterning (e.g., a blanket plasma etch) is performed to remove portions of the dielectric spacer layer 320, including the laterally-extending dielectric spacer layer base 326 and portions of the dielectric spacer layer 320 outside (above) the tub opening 304, leaving the dielectric sidewall spacer 136 on the bottom electrode cup sidewall 122.

Next, as shown in Figure 3E, an insulator layer 330 is deposited over the structure and extending down into an opening 332 (defined by the bottom electrode cup base 120 and dielectric sidewall spacer 136) to form the insulator cup 108. The insulator cup 108 includes (a) the laterally-extending insulator cup base 130 formed on the laterally-extending bottom electrode cup base 120 and (b) the insulator cup sidewall 132 extending upwardly from the laterally-extending insulator cup base 130 and formed laterally adjacent the dielectric sidewall spacer 136. In this example, the insulator cup sidewall 132 extends upwardly from a lateral perimeter edge of the laterally-extending insulator cup base 130. Due to the presence of the dielectric sidewall spacer 136, the laterally-extending insulator cup base 130 covers only a partial area of the laterally-extending bottom electrode cup base 120. In some examples, insulator layer 330 comprises silicon nitride (SiN) deposited with a thickness in the range of 250A-750A by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Alternatively, insulator layer 330 may comprise AI2O3, ZrCh, HfCb, ZrSiOx, HfSiOx, HfAlOx, or Ta2O5, or other suitable capacitor insulator material deposited using an Atomic Layer Deposition (ALD) process.

Next, as shown in Figure 3F, a top electrode layer 340 is deposited over the insulator layer 330 and extends into and fills an opening 342 defined by the insulator cup 108. In some examples, top electrode layer 340 may comprise Al, Ti, TiN, W, or a combination thereof, for example TiN and Al, and may be deposited by a physical vapor deposition (PVD) process.

Next, as shown in Figures 3G and 3H, a planarization process, e.g., chemical mechanical planarization (CMP) process, is performed to remove upper portions of the top electrode layer 340, insulator layer 330, and conformal metal layer 310, along with an upper portion of the dielectric sidewall spacer 136. Figure 3G shows a top view of the resulting structure after the planarization process, and Figure 3H shows a side cross-sectional view taking through line 3H-3H shown in Figure 3G. The planarization process defines a final form of the bottom electrode cup 106, insulator cup 108, dielectric sidewall spacer 136, and top electrode 110. The planarization process defines a planarized top surface 350 including a planarized top surface 352 of the top electrode 110 and a planarized top surface 354 of the bottom electrode cup sidewall 122.

As shown in Figure 3G, the bottom electrode cup sidewall 122, the dielectric sidewall spacer 136, and the insulator cup sidewall 132 have a respective closed-loop rectangular perimeter in the x-y plane. The dielectric sidewall spacer 136 physically separates the insulator cup sidewall 132 from the bottom electrode cup sidewall 122 around the closed-loop rectangular perimeter of the insulator cup sidewall 132.

Also shown in Figure 3G, interconnect vias 206 may have a circular shape in the x-y plane. In other examples, interconnect vias 206 may have any other shape in the x-y plane, e.g., a square or rectangular shape.

Next, as shown in Figures 31 and 3 J, an upper metal layer (M _x +i layer) may be formed on the planarized upper surface 350 of the via layer V _x . Figure 31 shows a top view of the resulting structure after formation of the upper metal layer, and Figure 3 J shows a side cross- sectional view taking through line 3 J-3 J shown in Figure 31. Various metal elements are formed in the upper metal layer M _x +i (e.g., by a metal deposition, pattern, and etch process) including (a) the upper interconnect element 210 connected to interconnect vias 206, (b) the top electrode connection pad 112 connected to the top electrode 110, and (c) the bottom electrode connection pad 114 connected to the bottom electrode cup 106. The upper metal layer M _x +i may comprise aluminum or other suitable metal.

As shown, the top electrode connection pad 112 may be formed directly on the planarized top surface 352 of the top electrode 110, and the bottom electrode connection pad 114 may be formed directly on the planarized top surface 354 of the bottom electrode cup sidewall 122. In this example, as shown in Figure 3G, the bottom electrode connection pad 114 has a closed-loop rectangular shape extending around a perimeter of the top electrode connection pad 112 in the x-y plane, and separated from the perimeter of the top electrode connection pad 112 by dielectric sidewall spacer 136, which similarly has a closed-loop rectangular shape extending around a perimeter of the top electrode connection pad 112 in the x-y plane. As discussed above, the presence of the dielectric sidewall spacer 136 to space the insulator cup sidewall 132 away from the bottom electrode cup sidewall 122 (in the x-y plane) allows both the top electrode connection pad 112 and bottom electrode connection pad 114 to be formed in the same upper metal layer (M _x +i layer) and directly on top of the top electrode 110 and bottom electrode cup sidewall 122, respectively.

Figure 4 is a side cross-sectional view showing an example IC structure 400 including an MIM capacitor module 402 and an interconnect structure 404 formed on a lower metal layer Mx comprising a silicided polysilicon layer. In this example, a lower interconnect element 408 of interconnect structure 404 and a bottom electrode base 406 of the MIM capacitor module 402 may each comprises a metal silicide region formed on a respective polysilicon region. In particular, the lower interconnect element 408 comprises a first metal silicide region 422a formed on a first polysilicon region 420a, and bottom electrode base 406 comprises a second metal silicide region 422b formed on a second poly silicon region 420b.