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Title:
METAL-INSULATOR-SEMICONDUCTOR TRANSISTORS WITH GATE-DIELECTRIC/SEMICONDUCTOR INTERFACIAL PROTECTION LAYER
Document Type and Number:
WIPO Patent Application WO/2018/036413
Kind Code:
A1
Abstract:
Structures, devices and methods are provided for forming an interface protection layer (204) adjacent to a fully or partially recessed gate structure (202) of a group III nitride, a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device or a metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming a gate dielectric (114) disposed on the interface protection layer (204).

Inventors:
CHEN JING (CN)
HUA MENGYUAN (CN)
Application Number:
PCT/CN2017/097646
Publication Date:
March 01, 2018
Filing Date:
August 16, 2017
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Assignee:
UNIV HONG KONG SCI & TECH (CN)
International Classes:
H01L29/778
Foreign References:
US20160133738A12016-05-12
CN104011867A2014-08-27
CN104078505A2014-10-01
CN104051458A2014-09-17
Attorney, Agent or Firm:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS (CN)
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