[0001] The invention concerns a metastability based random number generator intended especially for generating truly random numbers and series.

[0002] From the publication of the Polish patent PL 225188 Bl, there is known in the art a metastability based random number generator comprising a metastable generator of time intervals having at least two outputs and comprising at least one arbiter connected to at least two selected outputs of the metastable generator of time intervals .

[0003] From the same patent publication there is known a metastability based random number generator, having an output sub ^¬ system connected to outputs of the arbiter circuits .

[0004] From the publication of the Polish patent PL 225185 Bl, there is known in the art a metastability based random number generator comprising a number of multivibrators, having clock inputs connected with each other and connected to a first input of the generator, and having data inputs connected with each other and the data input of the first multivibrator in the series is connected to a second input of the generator. Generator has delays connected between selected data inputs of the multivibrators and at least one arbiter connected to at least two selected outputs of the multivibrators. An output sub-system is connected to outputs of the arbiter circuits .

[0005] From the publication of the Polish patent PL 225186 Bl, there is known in the art a metastable generator of time intervals comprising at least two multivibrators, having outputs connected to outputs of the generator and inputs connected to inputs of the generator .

[0006] From the publication of the Polish patent PL 224925 Bl, there is known in the art an arbiter circuit comprising two flip- flops. First input of the arbiter circuit is connected to both a data input of the first flip-flop and to a clock input of the second flip-flop. Second input of the arbiter circuit is connected to both a data input of the second flip-flop and to a clock input of the first flip-flop. A preset inputs of the flip-flops are connected to a control input of the arbiter circuit . Outputs of the flip-flops are outputs of the arbiter circuit.

[0007] From the same patent publication there is known an arbiter circuit, having the outputs of the flip-flops connected to the outputs of the arbiter circuit through a metastability filter, which comprises at least one flip-flop.

[0008] From the same patent publication there is known an arbiter circuit, having the outputs of the flip-flops connected to the outputs of the arbiter circuit through a randomness correction circuit, which comprises at least one flip-flop.

[0009] From the same patent publication there is known an arbiter circuit, having the outputs of the flip-flops connected to the outputs of the arbiter circuit through a metastability filter, whereas the outputs of the metastability filter are connected to the outputs of the arbiter circuit through a randomness correction circuit. Both the metastability filter and the randomness correction circuit comprise at least one flip-flop.

[0010] The aim of the invention is the mutual adjustment of the statistical properties of individual outputs of the block for metastability generation of time intervals, the adjustment of the block for metastability generation of time intervals to the arbiter circuits, the adjustment of particular stages of the arbiter circuits and both the mutual adjustment of the statistical properties of individual outputs of the block for metastability generation of time intervals and adjustment of the block for metastability generation of time intervals to arbiter circuits.

[0011] In the metastability based random number generator comprising a block for metastability generation of time intervals having at least two outputs and a block of arbiter circuits having at least two inputs connected to the outputs of the block for metastability generation of time intervals, providing an output signal of the generator, according to the invention at least one block is a block with regulated speed and is equipped with at least one speed control input connected to a speed control system. The effect of using such a construction allows to adjust one block in relation to the other block in terms of speed.

[0012] Advantageously the block for metastability generation of time intervals with regulated speed has a speed regulation of at least one output and it has at least one input regulating this speed. Such a solution allows to compensate differences in the operation of different intervals outputs and to adapt the generation conditions of the block to changing environmental conditions or attacks .

[0013] Metastability based random number generator advantageously comprises a speed adjustment circuit, having at least one output connected to at least one speed control input of the block for metastability generation of time intervals with regulated speed. Speed adjustment circuit allows to compensate differences in operation of the multivibrators.

[0014] Metastability based random number generator advantageously comprises a speed control system, having at least one generation speed control output connected to at least one speed control input of the block for metastability generation of time intervals with regulated speed. Speed control system allows to identify changing conditions and to detect attacks on the circuit, in which the metastability based random number generator according to the invention is used.

[0015] Advantageously the speed control system is connected to the block for metastability generation of time intervals with regulated speed through a controlled speed adjustment circuit, having at least one output connected to at least one speed control input of the block for metastability generation of time intervals with regulated speed, and at least one input of the controlled speed adjustment circuit is connected to at least one generation speed control output of the speed control system. Such a construction allows simultaneously to do the compensation and the adjustment of particular subcircuits.

[0016] Advantageously the block for metastability generation of time intervals with regulated speed comprises at least two multivibrators, having outputs connected to outputs of the block, and inputs connected to inputs of the block. Further at least one multivibrator is an adjustable speed multivibrator, having a speed control input connected to an speed control input of the block for metastability generation of time intervals with regulated speed.

[0017] Advantageously the block for metastability generation of time intervals comprises a number of multivibrators, having clock inputs connected, and data inputs connected, whereas a delay is connected between the inputs of at least two multivibrators, and at least one of the multivibrators is an adjustable speed multivibrator .

[0018] Advantageously the adjustable speed oscillatory response multivibrator comprises at least one voltage-mode multivibrator, having a supply voltage connected to a speed control input of the multivibrator. Such a construction allows to regulate the speed by the value of the supply voltage of the voltage-mode gates .

[0019] Advantageously the adjustable speed oscillatory response multivibrator comprises at least one current-mode multivibrator, having regulated current source connected to a speed control input of the multivibrator. Such a construction allows to regulate the speed by the value of the supply current of the current-mode gates.

[0020] In the block of arbiter circuits advantageously at least one arbiter circuit is a variable speed arbiter circuit. Further the block of arbiter circuits has at least one arbitration speed control input connected to at least one input of at least one variable speed arbiter circuit . Such a solution allows to adjust the speed of the arbiter circuit in relation to the previous circuit .

[0021] Advantageously the metastability based random number generator comprises a speed control system, having at least one arbitration speed control output connected to at least one arbitration speed control input. Speed control system allows to identify changing conditions and to detect attacks on the circuit, in which the metastability based random number generator according to the invention is used. [0022] Advantageously at least one variable speed arbiter circuit comprises two flip-flops, whereas a first input of the arbiter circuit is connected to both a data input of the first flip-flop and to a clock input of the second flip-flop, a second input of the arbiter circuit is connected to both a data input of the second flip-flop and to a clock input of the first flip-flop, whereas a control input of the arbiter circuit is connected to preset inputs of the flip-flops, and outputs of the arbiter circuit are connected to outputs of the flip-flops. Further at least one flip-flop is an adjustable speed flip-flop and is connected to the arbitration speed control input of the variable speed arbiter circuit .

[0023] Advantageously the outputs of at least one arbiter circuit are connected to the outputs of the flip-flops through a metastability filter comprising at least one adjustable speed flip-flop.

[0024] Advantageously at least one arbiter circuit is equipped at the output with a randomness correction circuit comprising at least one adjustable speed flip-flop.

[0025] Advantageously at least one adjustable speed flip-flop comprises at least one voltage-mode flip-flop, having a supply voltage connected to a speed control input of the flip-flop. Such a construction allows to regulate the speed by the value of the supply voltage of the voltage-mode gates.

[0026] Advantageously at least one adjustable speed flip-flop comprises at least one current-mode flip-flop, having regulated current source connected to a speed control input of the flip- flop. Such a construction allows to regulate the speed by the value of the supply current of the current-mode gates .

[0027] Speed control system advantageously comprises at least one input connected to at least one output of the metastability based random number generator. Such a solution allows the speed control system to control the quality of the generated numbers.

[0028] The invention enables the mutual adjustment of the statistical properties of the generated time intervals, enables simultaneous regulation of the speed of all outputs of the block for metastability generation of time intervals and regulation of the speed of arbiter circuits and particular stages of the arbiter circuits as well as enables both mutual adjustment of statistical properties of generated time intervals and mutual speed adjustment of block for metastability generation of time intervals and arbiter circuit or circuits .

[0029] The invention has been described below in detail, with reference to the attached figures. Fig.l presents a block diagram of metastability based random number generator comprising single arbiter circuit and block for metastability generation of time intervals connected to speed adjustment circuit, fig.2 presents a block diagram of metastability based random number generator comprising block of arbiter circuits with output sub-system and block for metastability generation of time intervals connected to speed adjustment circuit, fig.3 presents a block diagram of metastability based random number generator comprising block for metastability generation of time intervals and single arbiter circuit connected to speed control system, fig. presents a block diagram of metastability based random number generator comprising block of arbiter circuits with output sub-system and block for metastability generation of time intervals connected to speed control system connected to block of arbiter circuits and block for metastability generation of time intervals, fig.5 presents a block diagram of metastability based random number generator comprising single arbiter circuit and block for metastability generation of time intervals connected to speed control system and controlled speed adjustment circuit, fig.6 presents a block diagram of metastability based random number generator comprising block of arbiter circuits with output sub-system and block for metastability generation of time intervals connected to controlled speed adjustment circuit and speed control system, fig.7 presents a block diagram of metastability based random number generator comprising block for metastability generation of time intervals comprising multivibrators connected to controlled multivibrators adjustment circuit, fig.8 presents a block diagram of metastability based random number generator comprising block for metastability generation of time intervals comprising multivibrators and speed control system connected to arbiter circuits, fig.9 presents a block diagram of metastability based random number generator comprising block for metastability generation of time intervals comprising multivibrators and speed control system connected to arbiter circuits and multivibrators, fig.10 presents a block diagram of metastability based random number generator comprising block for metastability generation of time intervals comprising multivibrators and controlled multivibrators adjustment circuit and speed control system, fig.11 presents a block diagram of metastability based random number generator comprising block for metastability generation of time intervals comprising multivibrators, controlled multivibrators adjustment circuit and speed control system connected to outputs of the generator, fig.12 presents a block diagram of block for metastability generation of time intervals with individual speed control of multivibrators, fig.13 presents a block diagram of block for metastability generation of time intervals with mutual speed control of multivibrators, fig.14 presents a block diagram of voltage-mode adjustable speed multivibrator, fig.15 presents a block diagram of current-mode adjustable speed multivibrator, fig.16 presents a block diagram of single-stage variable speed arbiter circuit, fig.17 presents a block diagram of variable speed arbiter circuit with metastability filter, fig.18 presents a block diagram of variable speed arbiter circuit with randomness correction circuit, fig.19 presents a block diagram of variable speed arbiter circuit with metastability filter and randomness correction circuit, fig.20 presents a block diagram of voltage- mode adjustable speed flip-flop, and fig.21 presents a block diagram of current-mode adjustable speed flip-flop.

[0030] Metastability based random number generator presented in fig.l comprises a block for metastability generation of time intervals with regulated speed GMICRS having two outputs Ta and Tb connected to a block of arbiter circuits, which consists of one arbiter circuit A having two outputs LL and PLL, which are both outputs of the metastability based random number generator. The block for metastability generation of time intervals with regulated speed GMICRS has two speed control inputs RSa and RSb, which are connected to two outputs DSa and DSb of a speed adjustment circuit UDS.

[0031] The block for metastability generation of time intervals with regulated speed generates two signals that are metastable states resolves of the multivibrators. The arbiter circuit acts as a priority detector of the two signals that have been connected to its inputs. The speed adjustment allows to compensate differences in the operation of the multivibrators, which are most often caused by technological spreads in the production process, various types of material defects or other imperfections. The purpose of the compensation is to balance the statistical properties of the generated time intervals so that an interval of one multivibrator would be greater than an interval of another multivibrator with the probability of 0.5.

[0032] Metastability based random number generator presented in fig.2 comprises a block for metastability generation of time intervals with regulated speed GMICRS' having five outputs Tl, T2, T3, T4 and T5 connected to a block of arbiter circuits A' comprising three arbiter circuits Al, A2 and A3. The first arbiter circuit Al is connected to the first output Tl and to the second output T2 of the block for metastability generation of time intervals with regulated speed GMICRS', the second arbiter circuit A2 is connected to the second output T2 and to the third output T3 of the block for metastability generation of time intervals with regulated speed GMICRS', and the third arbiter circuit A3 is connected to the fourth output T4 and to the fifth output T5 of the block for metastability generation of time intervals with regulated speed GMICRS' . Each of the arbiter circuits comprises a pair of single outputs. The pairs of single outputs of the three arbiter circuits are connected to three pairs of single inputs of a output sub-system UK, which has two outputs LL' and PLL' , which are both outputs of the metastability based random number generator. The block for metastability generation of time intervals with regulated speed GMICRS' has five speed control input RSI, RS2, RS3, RS4 and RS5, which are connected to five outputs DS1, DS2, DS3 , DS4 and DS5 of the speed adjustment circuit UDS' .

[0033] The block for metastability generation of time intervals with regulated speed GMICRS' generates five signals that are metastable states resolves of the multivibrators. The arbiter circuits Al, A2 and A3 act as a priority detectors of pairs of signals that have been connected to their inputs. The speed adjustment allows to compensate differences in the operation of the multivibrators, which are most often caused by technological spreads in the production process, various types of material defects or other imperfections. The purpose of the compensation is to select the statistical properties of the generated time intervals so that in practice would be chosen the pairs of outputs of the block for metastability generation of time intervals with regulated speed, which allow to obtain the best statistical properties .

[0034] Metastability based random number generator presented in fig.3 comprises a block for metastability generation of time intervals GMIC having two outputs Ta and Tb connected to a block of variable speed arbiter circuits, which consists of one variable speed arbiter circuit ARS having two outputs LL and PLL, which are both outputs of the metastability based random number generator. The variable speed arbiter circuit ARS has a speed control input RSA connected to an arbitration speed control output SSA of the speed control system USS.

[0035] The block for metastability generation of time intervals GMIC generates two signals that are metastable states resolves of the multivibrators. The variable speed arbiter circuit ARS acts as a priority detector of the two signals that have been connected to its inputs . The speed adjustment of the variable speed arbiter circuit ARS allows matching it in relation to the block for metastability generation of time intervals GMIC. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. The speed control system USS analyzes the environmental measurements, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series .

[0036] Metastability based random number generator presented in fig.4 comprises a block for metastability generation of time intervals with regulated speed GMICRS' having five outputs Tl, T2, T3, T4 and T5 connected to a block of variable speed arbiter circuits ARS' comprising three arbiter circuits, whereas two of them are variable speed arbiter circuits ARSl, ARS2. The first variable speed arbiter circuit ARSl is connected to the first output Tl and to the second output T2 of the block for metastability generation of time intervals with regulated speed GMICRS' , the second variable speed arbiter circuit ARS2 is connected to the second output T2 and to the third output T3 of the block for metastability generation of time intervals with regulated speed GMICRS' , and the arbiter circuit A3 is connected to the fourth output T4 and to the fifth output T5 of the block for metastability generation of time intervals with regulated speed GMICRS' . Each of the arbiter circuits comprises a pair of single outputs. The pairs of single outputs of the three arbiter circuits are connected to three pairs of single inputs of a output sub-system UK, which has two outputs LL' and PLL' , which are both outputs of the metastability based random number generator. The block for metastability generation of time intervals with regulated speed GMICRS' has a speed control input RSG connected to an generation speed control output SSG' of the speed control system USS' . The variable speed arbiter circuits ARSl and ARS2 have speed control inputs RSA1 and RSA2 connected to an arbitration speed control output SSA' of the speed control system USS' . [0037] Block for metastability generation of time intervals with regulated speed GMICRS' generates five signals that are metastable states resolves of the multivibrators. The arbiter circuits ARS1, ARS2 and A3 act as a priority detectors of pairs of signals that have been connected to their inputs. The speed control of the block for metastability generation of time intervals with regulated speed GMICRS' and the variable speed arbiter circuits ARS1 and ARS2 allows adjusting of those circuits in relation to each other and in regard to the arbiter circuit A3. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. The speed control system USS' analyzes the environmental measurements, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series.

[0038] Metastability based random number generator presented in fig.5 comprises a block for metastability generation of time intervals with regulated speed GMICRS having two outputs Ta and Tb connected to a block of variable speed arbiter circuits, which consists of one variable speed arbiter circuit ARS' having two outputs LL and PLL, which are both outputs of the metastability based random number generator. The block for metastability generation of time intervals with regulated speed GMICRS has two speed control inputs RSa and RSb connected to two outputs DSa and DSb of the controlled speed adjustment circuit RUDS. The controlled speed adjustment circuit RUDS has a generation speed control input RSG' connected to generation speed control output SSG of the speed control system USS. The variable speed arbiter circuit ARS' has two speed control inputs RSAa and RSAb connected to two arbitration speed control outputs SSAa and SSAb of the speed control system USS .

[0039] Block for metastability generation of time intervals with regulated speed GMICRS generates two signals that are metastable states resolves of the multivibrators. The variable speed arbiter circuit ARS' acts as a priority detector of the two signals that have been connected to its inputs. The speed adjustment of the particular outputs of the block for metastability generation of time intervals with regulated speed GMICRS, which the controlled speed adjustment circuit RUDS performs, allows to compensate differences in the operation of the multivibrators, which are most often caused by technological spreads in the production process, various types of material defects or other imperfections. The purpose of the compensation is to balance the statistical properties of the generated time intervals so that an interval of one multivibrator would be greater than an interval of another multivibrator with the probability of 0.5. However the speed control of the whole block for metastability generation of time intervals with regulated speed GMICRS is performed with the use of the controlled speed adjustment circuit RUDS based on a signal at the generation speed control input RSG' . The connection of two speed control signals RSAa and RSAb to the variable speed arbiter circuit allows better speed regulation through the control of particular stages of the arbiter circuit ARS. The mutual speed adjustment of the block for metastability generation of time intervals with regulated speed GMICRS and subsequent stages of the variable speed arbiter circuit ARS allows to match these circuits with each other. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. The speed control system USS analyzes the environmental measurements, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series.

[ 0040 ] Metastability based random number generator presented in fig.6 comprises a block for metastability generation of time intervals with regulated speed GMICRS' having five outputs Tl, T2, T3, T4 and T5 connected to a block of variable speed arbiter circuits ARS' comprising three variable speed arbiter circuits ARSl, ARS2 and ARS 3. The first variable speed arbiter circuit ARSl is connected to the first output Tl and to the second output T2 of the block for metastability generation of time intervals with regulated speed GMICRS', the second variable speed arbiter circuit ARS2 is connected to the second output T2 and to the third output T3 of the block for metastability generation of time intervals with regulated speed GMICRS' , and the third variable speed arbiter circuit ARS3 is connected to the fourth output T4 and to the fifth output T5 of the block for metastability generation of time intervals with regulated speed GMICRS' . Each of the variable speed arbiter circuits comprises a pair of single outputs. The pairs of single outputs of the three variable speed arbiter circuits are connected to three pairs of single inputs of a output sub-system UK, which has two outputs LL' and PLL' , which are both outputs of the metastability based random number generator. The block for metastability generation of time intervals with regulated speed GMICRS' has fife speed control inputs RSI, RS2, RS3, RS4 and RS5 connected to five outputs DS1, DS2, DS3, DS4 and DS5 of the controlled speed adjustment circuit RUDS' . The controlled speed adjustment circuit RUDS' has a generation speed control input RSG' connected to an generation speed control output SSG' of the speed control system USS' . The variable speed arbiter circuits ARSl, ARS2 and ARS 3 have speed control inputs RSA1, RSA2 and RSA3 connected to an arbitration speed control output SSA' of the speed control system USS' . Outputs LL' and PLL' of the output sub-system UK are connected to inputs WLL' and PLL' of the speed control system USS' .

[0041] Block for metastability generation of time intervals with regulated speed GMICRS' generates five signals that are metastable states resolves of the multivibrators. The variable speed arbiter circuits ARSl, ARS2 and ARS3 act as a priority detectors of pairs of signals that have been connected to their inputs. The speed adjustment of the particular outputs of the block for metastability generation of time intervals with regulated speed GMICRS' , which the controlled speed adjustment circuit RUDS' performs, allows to compensate differences in the operation of the multivibrators, which are most often caused by technological spreads in the production process, various types of material defects or other imperfections. The purpose of the compensation is to select the statistical properties of the generated time intervals so that in practice would be chosen the pairs of outputs of the block for metastability generation of time intervals with regulated speed, which allow to obtain the best statistical properties. However the speed control of the whole block for metastability generation of time intervals with regulated speed GMICRS' is performed with the use of the controlled speed adjustment circuit RUDS' based on a signal at the generation speed control input RSG' . The mutual speed adjustment of the block for metastability generation of time intervals with regulated speed GMICRS' and the variable speed arbiter circuits ARS1, ARS2 and ARS3 allows to match these circuits with each other. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. The speed control system USS' analyzes statistics of generated numbers and series, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series.

[ 0042 ] Metastability based random number generator presented in fig.7 comprises a block for metastability generation of time intervals with regulated speed GMICRS' comprising a series of six adjustable speed multivibrators MRS1, MRS2 , MRS3, MRS4 , MRS5 and MRS6 in the form of "D" flip-flops, having clock inputs CI, C2, C3, C4, C5 and C6 connected with each other and connected to the first input of the generator II, and having data inputs Dl, D2, D3, D4, D5 and D6 connected with each other through delays Ul, U2, U3, U4 and U5, and the data input Dl of the first adjustable speed multivibrator MRS1 in the series is connected to the second input of the generator 12. Outputs of the six adjustable speed multivibrators Ql, Q2 , Q3, Q4, Q5 and Q6 are connected to inputs of the block of arbiter circuits A' comprising five arbiter circuits Al, A2, A3, A4 and A5. The first arbiter circuit Al is connected to the data output Ql of the first adjustable speed multivibrator MRS1 and the data output Q2 of the second adjustable speed multivibrator MRS2, the second arbiter circuit A2 is connected to the data output Q2 of the second adjustable speed multivibrator MRS2 and the data output Q3 of the third adjustable speed multivibrator MRS3, the third arbiter circuit A3 is connected to the data output Q3 of the third adjustable speed multivibrator MRS3 and the data output Q4 of the fourth adjustable speed multivibrator MRS4, the fourth arbiter circuit A4 is connected to the data output Q4 of the fourth adjustable speed multivibrator MRS4 and the data output Q5 of the fifth adjustable speed multivibrator MRS5, and the fifth arbiter circuit A5 is connected to the data output Q5 of the fifth adjustable speed multivibrator MRS5 and the data output Q6 of the sixth adjustable speed multivibrator MRS 6. Each of the multivibrators MRS1, MRS2 , MRS 3, MRS4, MRS 5 and MRS 6 has a speed control input RSI, RS2, RS3, RS4, RS5 and RS6, and those inputs are subsequently connected to speed adjustment outputs DS1, DS2, DS3, DS4, DS5 and DS6 of the multivibrators adjustment circuit UDM. Each of the arbiter circuits Al, A2 , A3, A4 and A5 has a pair of single outputs. The pairs of single outputs of the five arbiter circuits are connected to five pairs of single inputs of the output sub-system UK, which has two outputs LL and PLL being outputs of the metastability based random number generator.

[0043] Propagation times caused by the delays are small and usually chosen so that some of the flip flops in the middle of the series operate in the neighborhood of the metastable point . The arbiter circuits act as a priority detectors of pairs of signals that have been connected to their inputs. The first outputs of the arbiter circuits give information about which signal came earlier - thay are also the outputs of binary random numbers. The second outputs of the arbiter circuits carry information about the correctness of random numbers on the first outputs of the arbiter circuits. The output sub-system UK collects the single random numbers from the arbiter circuits and the result of the operation on these numbers is set up on the first output LL . The second output PLL of the output sub-system UK carries information about the correctness of the data on the first output. The speed regulation made by the multivibrators adjustment circuit UDM allows to compensate differences in the operation of the multivibrators, which are most often caused by technological spreads in the production process, various types of material defects or other imperfections. The purpose of the compensation is to select the statistical properties of the generated time intervals so that in practice would be chosen the pairs of outputs of the block for metastability generation of time intervals with regulated speed, which allow to obtain the best statistical properties .

[ 0044 ] Metastability based random number generator presented in fig.8 comprises a block for metastability generation of time intervals GMIC comprising a series of six multivibrators Ml, M2, M3, M4, M5 and M6 in the form of ,,D" flip-flops, having clock inputs CI, C2, C3, C4, C5 and C6 connected with each other and connected to a first input of the generator II, and having data inputs Dl, D2, D3, D4, D5 and D6 connected with each other through delays Ul, U2 , U3, U4 and U5, and the data input Dl of the first multivibrator Ml in the series is connected to a second input of the generator 12. Outputs of the six multivibrators Ql, Q2, Q3, Q4, Q5 and Q6 are connected to inputs of a block of variable speed arbiter circuits ARS' comprising five variable speed arbiter circuits ARS1, ARS2 , ARS3 , ARS4 and ARS5. The first variable speed arbiter circuit ARS1 is connected to the data output Ql of the first multivibrator Ml and the data output Q2 of the second multivibrator M2, the second variable speed arbiter circuit ARS2 is connected to the data output Q2 of the second multivibrator M2 and the data output Q3 of the third multivibrator M3, the third variable speed arbiter circuit ARS3 is connected to the data output Q3 of the third multivibrator M3 and the data output Q4 of the fourth multivibrator M4, the fourth variable speed arbiter circuit ARS4 is connected to the data output Q4 of the fourth multivibrator M4 and the data output Q5 of the fifth multivibrator M5, and the fifth variable speed arbiter circuit ARS5 is connected to the data output Q5 of the fifth multivibrator M5 and the data output Q6 of the sixth multivibrator M6. Variable speed arbiter circuits ARS1, ARS2, ARS3, ARS4 and ARS5 have speed control inputs RSA1 , RSA2, RSA3, RSA4 and RSA5, which are connected to arbitration speed control output SSA of the speed control system USS. Each of the variable speed arbiter circuits ARS1, ARS2, ARS3, ARS4 and ARS5 has a pair of single outputs, which are connected to five pairs of single inputs of the output sub-system UK. The output sub-system UK has two outputs LL and PLL being outputs of the metastability based random number generator.

[0045] The speed regulation of the variable speed arbiter circuits ARS1, ARS2, ARS3, ARS4 and ARS5 allows to adjust their operation in regard to the multivibrators and the output sub-system UK. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. The speed control system USS analyzes the environmental measurements, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series .

[0046] Metastability based random number generator presented in fig.9 comprises a block for metastability generation of time intervals with regulated speed GMICRS' comprising a series of six multivibrators Ml, M2, M3, MRS4, MRS5 and MRS 6 in the form of „D" flip-flops, three of them are adjustable speed multivibrators MRS 4 , MRS5 and MRS 6. Clock inputs CI, C2, C3, C4, C5 and C6 of all six multivibrators Ml, M2, M3, MRS 4 , MRS 5 and MRS 6 are connected with each other and connected to a first input of the generator II, whereas data inputs Dl, D2, D3, D4, D5 and D6 are connected with each other through delays Ul, U2 , U3, U4 and U5, and the data input Dl of the first multivibrator Ml in the series is connected to a second input of the generator 12. Outputs of all six multivibrators Ql, Q2 , Q3, Q4, Q5 and Q6 are connected to inputs of the block of variable speed arbiter circuits ARS' comprising five variable speed arbiter circuits ARSl, ARS2, ARS3, ARS4 and ARS5. The first variable speed arbiter circuit ARSl is connected to the data output Ql of the first multivibrator Ml and the data output Q2 of the second multivibrator M2, the second variable speed arbiter circuit ARS2 is connected to the data output Q2 of the second multivibrator M2 and the data output Q3 of the third multivibrator M3, the third variable speed arbiter circuit ARS3 is connected to the data output Q3 of the third multivibrator M3 and the data output Q4 of the fourth multivibrator MRS4, the fourth variable speed arbiter circuit ARS4 is connected to the data output Q4 of the fourth multivibrator MRS4 and the data output Q5 of the fifth multivibrator MRS5, and the fifth variable speed arbiter circuit ARS5 is connected to the data output Q5 of the fifth multivibrator MRS5 and the data output Q6 of the sixth multivibrator MRS6. Each of the adjustable speed multivibrators MRS4 , MRS5 and MRS 6 has a speed control input RS , RS5 and RS6, and those inputs are connected to a multivibrators speed control output SSM of the speed control system USS. The variable speed arbiter circuits ARSl, ARS2, ARS3 , ARS4 and ARS5 have speed control inputs RSA1, RSA2, RSA3, RSA4 and RSA5, which are connected to arbitration speed control output SSA of the speed control system USS. Each of the variable speed arbiter circuits ARSl, ARS2, ARS3, ARS4 and ARS5 has a pair of single outputs, which are connected to five pairs of single inputs of the output sub-system UK. The output sub-system UK has two outputs LL and PLL being outputs of the metastability based random number generator.

[ 0047 ] The speed regulation of the adjustable speed multivibrators MRS4, MRS5 and MRS6 allows to influence only a part of the multivibrators in the series of all multivibrators Ml, M2, M3, MRS , MRS5 and MRS 6. Moreover the speed regulation of the variable speed arbiter circuits ARS1, ARS2, ARS3, ARS4 and ARS5 allows to adjust their operation with each other and in regard to the output sub-system UK. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit . The speed control system USS analyzes the environmental measurements, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series .

[0048] Metastability based random number generator presented in fig.10 comprises a block for metastability generation of time intervals with regulated speed GMICRS' comprising a series of six adjustable speed multivibrators MRS1, MRS2 , MRS3, MRS4, MRS 5 and MRS6 in the form of „D" flip-flops, having clock inputs CI, C2, C3, C4, C5 and C6 connected with each other and connected to a first input of the generator II, and having data inputs Dl, D2, D3, D4, D5 and D6 connected with each other through delays Ul, U2, U3, U4 and U5, and the data input Dl of the first adjustable speed multivibrator MRS1 in the series is connected to a second input of the generator 12. Outputs of the six adjustable speed multivibrators Ql, Q2 , Q3, Q4, Q5 and Q6 are connected to inputs of the block of variable speed arbiter circuits ARS' comprising five variable speed arbiter circuits ARS1, ARS2, ARS3, ARS4 and ARS5. The first variable speed arbiter circuit ARS1 is connected to the data output Ql of the first adjustable speed multivibrator MRS1 and the data output Q2 of the second adjustable speed multivibrator MRS2, the second variable speed arbiter circuit ARS2 is connected to the data output Q2 of the second adjustable speed multivibrator MRS2 and the data output Q3 of the third adjustable speed multivibrator MRS3, the third variable speed arbiter circuit ARS3 is connected to the data output Q3 of the third adjustable speed multivibrator MRS3 and the data output Q4 of the fourth adjustable speed multivibrator MRS4, the fourth variable speed arbiter circuit ARS4 is connected to the data output Q4 of the fourth adjustable speed multivibrator MRS4 and the data output Q5 of the fifth adjustable speed multivibrator MRS5, and the fifth variable speed arbiter circuit ARS5 is connected to the data output Q5 of the fifth adjustable speed multivibrator MRS5 and the data output Q6 of the sixth adjustable speed multivibrator MRS6. Each of the multivibrators MRS1, MRS2, MRS3, MRS4, MRS5 and MRS 6 has a speed control input RSI, RS2, RS3, RS4, RS5 and RS6, and those inputs are subsequently connected to speed adjustment outputs DS1, DS2, DS3, DS4, DS5 and DS6 of the controlled multivibrators adjustment circuit RUDM. The controlled multivibrators adjustment circuit RUDM has a multivibrators speed control input RSM connected to a multivibrators speed control output SSM of the speed control system USS. The variable speed arbiter circuits ARS1, ARS2, ARS3, ARS4 and ARS5 have speed control inputs RSA1, RSA2, RSA3, RSA4 and RSA5, which are connected to an arbitration speed control output SSA of the speed control system USS. Each of the variable speed arbiter circuits ARS1, ARS2 , ARS3, ARS4 and ARS5 has a pair of single outputs, which are connected to five pairs of single inputs of the output sub-system UK. The output sub-system UK has two outputs LL and PLL being outputs of the metastability based random number generator.

[0049] The speed regulation made by the controlled multivibrators adjustment circuit RUDM allows to compensate differences in the operation of the multivibrators, which are most often caused by technological spreads in the production process, various types of material defects or other imperfections. The purpose of the compensation is to select the statistical properties of the generated time intervals so that in practice would be chosen the pairs of outputs of the block for metastability generation of time intervals with regulated speed, which allow to obtain the best statistical properties. However the speed control of multiple multivibrators is performed based on a signal at the multivibrators speed control input RSM. The mutual speed adjustment of the multivibrators and arbiter circuits allows to match these circuits with each other. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. The speed control system USS analyzes the environmental measurements, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series.

[0050] Metastability based random number generator presented in fig.11 has the same construction as the one presented in fig.10, with the difference that the outputs LL and PLL of the output sub ^¬ system UK are connected to inputs WLL and WPLL of the speed control system USS.

[0051] The connection of the outputs of the output sub-system to the inputs of the speed control system USS allows the speed control system to additionally analyze statistics of generated random numbers and random series, on the basis of which it adjusts the speed in order to obtain the best properties of the circuit in terms of speed and randomness quality of generated numbers and series.

[0052] Block for metastability generation of time intervals with regulated speed presented GMICRS in fig.12 comprises two adjustable speed multivibrators MRS1 and MRS2 in the form of „D" flip-flops, each having one data input Dl and D2, one data output Ql and Q2 , one clock input CI and C2 and one speed control input RSI and RS2. The data inputs of the flip-flops Dl and D2 are connected with each other and connected to a first input II generation block GMICRS. The clock inputs of the flip-flops CI and C2 are connected with each other and connected to a second input 12 of the generation block GMICRS. The data output Ql of the first flip-flop MRS1 is connected to a first output 01 of the generation block GMICRS. The data output Q2 of the second flip-flop MRS2 is connected to a second output 02 of the generation block GMICRS. The generation block GMICRS has also two multivibrators adjustment inputs, whereas the first input RSI' is connected to a speed control input RSI of the first multivibrator MRSl, and the second input RS2' is connected to a speed control input RS2 of the second multivibrator MRS2.

[0053] The speed adjustment allows to compensate differences in the operation of the multivibrators, which are most often caused by technological spreads in the production process, various types of material defects or other imperfections. The purpose of the compensation is to balance the statistical properties of the generated time intervals so that an interval of one multivibrator would be greater than an interval of another multivibrator with the probability of 0.5.

[0054] Block for metastability generation of time intervals with regulated speed GMICRS presented in fig.13 comprises two adjustable speed multivibrators MRSl and MRS2 in the form of „D" flip-flops, each having one data input Dl and D2, one data output Ql and Q2 , one clock input CI and C2 and one speed control input RSI and RS2. The data inputs of the flip-flops Dl and D2 are connected with each other and connected to a first input II generation block GMICRS. The clock inputs of the flip-flops CI and C2 are connected with each other and connected to a second input 12 of the generation block GMICRS. The data output Ql of the first flip-flop MRSl is connected to a first output 01 of the generation block GMICRS. The data output Q2 of the second flip-flop MRS2 is connected to a second output 02 of the generation block GMICRS. The block GMICRS has a speed control input RS, which is connected to both the speed control input RSI of the first multivibrator MRSl and to the speed control input RS2 of the second multivibrator MRS2.

[0055] The speed control of the whole generation block allows to adjust it in regard to a circuit connected to the outputs of the generation block. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. [ 0056 ] Voltage-mode adjustable speed multivibrator presented in fig.14, included in a block for metastability generation of time intervals, comprise a voltage-mode multivibrator NM with two inputs D' and C connected to inputs D and C of the adjustable speed multivibrator MRS and an output Q' connected to an output Q of the adjustable speed multivibrator MRS. An input of the positive supply voltage VDD of the voltage-mode multivibrator NM is connected to a speed control input RS of the adjustable speed multivibrator MRS, whereas an input of the negative supply voltage VSS of the voltage-mode multivibrator NM is connected to general ground of the circuit GND .

[ 0057 ] The voltage-mode multivibrator NM in the form of "D" flip- flop, based on standard logical gates or CMOS technology, can be regulated in terms of speed by changing the power supply voltage of the flip-flop. Lower voltage means slower operation, whereas higher voltage means faster operation. The power supply voltage can be reduced even to the subthreshold voltage of the transistors. The maximum voltage is determined by the boundary parameters of the circuit operation.

[ 0058 ] Current-mode adjustable speed multivibrator presented in fig.15, included in a block for metastability generation of time intervals, comprise a regulated current source ISS and connected to it a logical block of the multivibrator LM with two inputs D' and C connected to inputs D and C of the adjustable speed multivibrator MRS and an output Q' connected to an output Q of the adjustable speed multivibrator MRS. A speed control input RS of the adjustable speed multivibrator MRS is connected to the regulated current source ISS. The source of the positive supply voltage is connected to the logical block of the multivibrator LM, and the general ground of the circuit is connected to the regulated current source ISS.

[ 0059 ] The multivibrator MRS made of current-mode gates can be regulated in terms of speed by changing the current value of these gates . Lower current means slower operation, whereas higher current means faster operation. Current sources in the form of current mirrors allow to easy and simultaneous control of multiple current sources .

[0060] Variable speed arbiter circuit presented in fig.16 comprises two adjustable speed flip-flops in the form of „D" flip- flops PRS1 and PRS2, each having one data input Dl and D2, one data output Ql and Q2, one clock input CI and C2 , one asynchronous reset input Rl and R2 and one speed control input RSI and RS2. A first input II of the variable speed arbiter circuit ARS is connected to both the data input Dl of the first adjustable speed flip-flop PRS1 and to the clock input C2 of the second adjustable speed flip-flop PRS2, a second input 12 of the arbiter circuit A is connected to both the data input D2 of the second adjustable speed flip-flop P2 and to the clock input CI of the first adjustable speed flip-flop PI. The outputs of the adjustable speed flip-flops Ql and Q2 are connected to the outputs of the variable speed arbiter circuit 01 and 02. A control input of the arbiter circuit WA is connected to the asynchronous reset inputs Rl and R2 of both adjustable speed flip-flops PRS1 and PRS2. The variable speed arbiter circuit ARS has also a speed control input RSA connected to the both speed control inputs RSI and RS2 of the both adjustable speed flip-flops PRS1 and PRS2.

[0061] The speed control of the flip-flops PRS1 and PRS2 , which form the first stage of the arbiter circuit, allows to adjust it in regard to a circuit connected to the its inputs II and 12. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit.

[0062] Variable speed arbiter circuit presented in fig.17 comprises two adjustable speed flip-flops in the form of "D" flip- flops PRS1 and PRS2, each having one data input Dl and D2, one data output Ql and Q2, one clock input CI and C2, one asynchronous reset input Rl and R2 and one speed control input RSI and RS2. The data inputs Dl and D2 and the clock inputs CI and C2 are connected to delays 0P1, 0P2, 0P3 and 0P4 so, that the data input Dl of the first adjustable speed flip-flop PRS1 is connected to an output of the first delay OP1, the clock input CI of the first adjustable speed flip-flop PRS1 is connected to an output of the second delay 0P2, the data input D2 of the second adjustable speed flip-flop PRS2 is connected to an output of the third delay OP3, and the clock input C2 of the second adjustable speed flip-flop PRS2 is connected to an output of the fourth delay 0P4. A first input II of the variable speed arbiter circuit ARS is connected to both an input of the first delay 0P1 and to an input of the fourth delay 0P4, a second input 12 of the variable speed arbiter circuit ARS is connected to both an input of the second delay 0P2 and to an input of the third delay 0P3. An control input of the variable speed arbiter circuit WA is connected to the asynchronous reset inputs Rl and R2 of the both adjustable speed flip-flops PRS1 and PRS2. The variable speed arbiter circuit ARS has also two control speed inputs RSA and RSA' , of which the first one RSA is connected to the both speed control inputs RSI and RS2 of the both adjustable speed flip-flops PRS1 and PRS2. The outputs of the flip-flops Ql and Q2 are connected to inputs FI1 and FI2 of a metastability filter FM, and outputs F01 and F02 of the metastability filter FM are connected to outputs of the variable speed arbiter circuit 01 and 02. The metastability filter FM comprises two adjustable speed flip-flops in the form of "D" flip-flops PRS3 and PRS4, each having one data input D3 and D4, one data output Q3 and Q4, one clock input C3 and C4 and one speed control input RS3 and RS4. The data inputs of these adjustable speed flip-flops D3 and D4 are connected to the inputs of the metastability filter FI1 and FI2, and the data outputs of the adjustable speed flip-flops Q3 and Q4 are connected to the outputs of the metastability filter F01 and F02. The clock inputs of the flip-flops C3 and C4 are connected to a second control input WF of the variable speed arbiter circuit ARS, whereas the both speed control inputs RS3 and RS4 of the both adjustable speed flip-flops PRS3 and PRS4 of the metastability filter FM are connected to a second control speed input RSA' of the variable speed arbiter circuit ARS. [0063] The delays OP1, OP2, OP3 and OP4, along with connected to them adjustable speed flip-flops PRS1 and PRS2, form the first stage of the arbiter circuit and the metastability filter FM is the second stage of the arbiter circuit. The speed of the first stage of the arbiter circuit is controlled by the first control speed input RSA, and the second stage of the arbiter circuit is controlled by the second control speed input RSA' . The speed control of the first stage of the arbiter circuit allows to adjust it in regard to a circuit connected to the its inputs II and 12, and the speed control of the second stage allows to adjust this stage in terms of speed in regard to the first stage. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit.

[0064] Variable speed arbiter circuit presented in fig.18 comprises two adjustable speed flip-flops in the form of "D" flip- flops PRS1 and PRS2, each having one data input Dl and D2, one data output Ql and Q2, one clock input CI and C2, one asynchronous reset input Rl and R2 and one speed control input RSI and RS2. The data inputs Dl and D2 and the clock inputs CI and C2 are connected to delays 0P1, 0P2, 0P3 and 0P4 so, that the data input Dl of the first adjustable speed flip-flop PRS1 is connected to an output of the first delay OP1, the clock input CI of the first adjustable speed flip-flop PRS1 is connected to an output of the second delay 0P2, the data input D2 of the second adjustable speed flip-flop PRS2 is connected to an output of the third delay 0P3, and the clock input C2 of the second adjustable speed flip-flop PRS2 is connected to an output of the fourth delay OP4. A first input II of the variable speed arbiter circuit ARS is connected to both an input of the first delay 0P1 and to an input of the fourth delay 0P4, a second input 12 of the variable speed arbiter circuit ARS is connected to both an input of the second delay OP2 and to an input of the third delay 0P3. An control input of the variable speed arbiter circuit A is connected to the asynchronous reset inputs Rl and R2 of the both adjustable speed flip-flops PRS1 and PRS2. The variable speed arbiter circuit ARS has also two control speed inputs RSA and RSA' , of which the first one RSA is connected to the both speed control inputs RSI and RS2 of the both adjustable speed flip-flops PRS1 and PRS2. The outputs of the flip-flops Ql and Q2 are connected to inputs UI1 and UI2 a randomness correction circuit UKL . The randomness correction circuit UKL comprises a flip-flop in the form of "JK" flip-flop JK and a parity detector XOR in the form of an „exclusive-or" gate. The flip-flop JK has two data inputs J and K, one data output JKQ and one clock input JKC . The parity detector XOR has two inputs and one output. The data inputs of the flip-flop J and K are connected to the inputs UI1 and UI2 of the randomness correction circuit UKL, and the data output of the flip-flop JKQ is connected to a first output U01 of the randomness correction circuit UKL. The inputs of the parity detector XOR are connected to the inputs UI1 and UI2 of the randomness correction circuit UKL, and the output of the parity detector XOR is connected to a second output U02 of the randomness correction circuit UKL. The clock input of the flip-flop JKC is connected to a second control input WU of the variable speed arbiter circuit ARS. Outputs UOl and U02 of the randomness correction circuit UKL are connected to outputs of the arbiter circuit 01 and 02.

[0065] The delays 0P1, OP2, OP3 and OP4, along with connected to them adjustable speed flip-flops PRS1 and PRS2, form the first stage of the arbiter circuit, and the randomness correction circuit UKL is the second stage of the arbiter circuit. The speed control of the first stage of the arbiter circuit is controlled by the speed control input RSA and it allows to adjust the arbiter circuit in regard to a circuit connected to the its inputs II and 12 and to the second stage of the arbiter circuit. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit. [0066] Variable speed arbiter circuit presented in fig.19 comprises two adjustable speed flip-flops in the form of "D" flip- flops PRS1 and PRS2, each having one data input Dl and D2, one data output Ql and Q2, one clock input CI and C2, one asynchronous reset input Rl and R2 and one speed control input RSI and RS2. The data inputs Dl and D2 and the clock inputs CI and C2 are connected to delays 0P1, 0P2, 0P3 and 0P4 so, that the data input Dl of the first adjustable speed flip-flop PRS1 is connected to an output of the first delay OP1, the clock input CI of the first adjustable speed flip-flop PRS1 is connected to an output of the second delay 0P2, the data input D2 of the second adjustable speed flip-flop PRS2 is connected to an output of the third delay 0P3, and the clock input C2 of the second adjustable speed flip-flop PRS2 is connected to an output of the fourth delay OP4. A first input II of the variable speed arbiter circuit ARS is connected to both an input of the first delay 0P1 and to an input of the fourth delay 0P4, a second input 12 of the variable speed arbiter circuit ARS is connected to both an input of the second delay 0P2 and to an input of the third delay 0P3. An control input of the variable speed arbiter circuit A is connected to the asynchronous reset inputs Rl and R2 of the both adjustable speed flip-flops PRS1 and PRS2. The variable speed arbiter circuit ARS has also two control speed inputs RSA and RSA' , of which the first one RSA is connected to the both speed control inputs RSI and RS2 of the both adjustable speed flip-flops PRS1 and PRS2. The outputs of the flip-flops Ql and Q2 are connected to inputs FI1 and FI2 of a metastability filter FM, and outputs FOl and F02 of the metastability filter FM are connected to inputs UI1 and UI2 of a randomness correction circuit UKL . The metastability filter FM comprises two adjustable speed flip-flops in the form of "D" flip-flops PRS3 and PRS4, each having one data input D3 and D4, one data output Q3 and Q4, one clock input C3 and C4 and one speed control input RS3 and RS4. The data inputs of these adjustable speed flip-flops D3 and D4 are connected to the inputs of the metastability filter FI1 and FI2, and the data outputs of the adjustable speed flip-flops Q3 and Q4 are connected to the outputs of the metastability filter F01 and F02. The clock inputs of the flip-flops C3 and C4 are connected to a second control input WF of the variable speed arbiter circuit ARS, whereas the both speed control inputs RS3 and RS4 of the both adjustable speed flip-flops PRS3 and PRS4 of the metastability filter FM are connected to a second control speed input RSA' of the variable speed arbiter circuit ARS. The randomness correction circuit UKL comprises a flip-flop in the form of "JK" flip-flop JK and a parity detector XOR in the form of an ,,exclusive-or" gate. The flip-flop JK has two data inputs J and K, one data output JKQ and one clock input JKC . The parity detector XOR has two inputs and one output. The data inputs of the flip-flop J and K are connected to the inputs UI1 and UI2 of the randomness correction circuit UKL, and the data output of the flip-flop JKQ is connected to a first output U01 of the randomness correction circuit UKL. The inputs of the parity detector XOR are connected to the inputs UI1 and UI2 of the randomness correction circuit UKL, and the output of the parity detector XOR is connected to a second output U02 of the randomness correction circuit UKL. The clock input of the flip-flop JKC is connected to a third control input U of the variable speed arbiter circuit ARS. Outputs UOl and U02 of the randomness correction circuit UKL are connected to outputs of the arbiter circuit 01 and 02.

[0067] The delays 0P1, 0P2, 0P3 and 0P4, along with connected to them adjustable speed flip-flops PRS1 and PRS2, form the first stage of the arbiter circuit. The metastability filter FM is the second stage of the arbiter circuit, and the randomness correction circuit UKL is the third stage of the arbiter circuit. The speed of the first stage of the arbiter circuit is controlled by the first control speed input RSA, and the second stage of the arbiter circuit is controlled by the second control speed input RSA' . The speed control of the first stage of the arbiter circuit allows to adjust it in regard to a circuit connected to the its inputs II and 12, and the speed control of the second stage allows to adjust this stage in terms of speed in regard to the first stage and the third stage of the arbiter circuit. Such an adjustment allows to minimize the harmful effects of various factors - for example, environmental factors, such as temperature or power supply voltage, or active side-channel attacks, aimed at disturbing the proper operation of the circuit.

[0068] Voltage-mode adjustable speed flip-flop presented in fig.20, included in a variable speed arbiter circuit, comprise a voltage-mode flip-flop NP with two inputs D' and C connected to inputs D and C of the adjustable speed flip-flop PRS and an output Q' connected to an output Q of the adjustable speed flip-flop PRS. An input of the positive supply voltage VDD of the voltage-mode flip-flop NP is connected to a speed control input RS of the adjustable speed flip-flop PRS, whereas an input of the negative supply voltage VSS of the voltage-mode flip-flop NP is connected to general ground of the circuit GND .

[0069] The voltage-mode flip-flop NP in the form of "D" flip- flop, based on standard logical gates or CMOS technology, can be regulated in terms of speed by changing the power supply voltage of the flip-flop. Lower voltage means slower operation, whereas higher voltage means faster operation. The power supply voltage can be reduced even to the subthreshold voltage of the transistors. The maximum voltage is determined by the boundary parameters of the circuit operation.

[0070] Current-mode adjustable speed flip-flop presented in fig.21, included in a variable speed arbiter circuit, comprise a regulated current source ISS and connected to it a logical block of the flip-flop LP with two inputs D' and C connected to inputs D and C of the adjustable speed flip-flop PRS and an output Q' connected to an output Q of the adjustable speed flip-flop PRS. A speed control input RS of the adjustable speed flip-flop PRS is connected to the regulated current source ISS. The source of the positive supply voltage is connected to the logical block of the flip-flop LP, and the general ground of the circuit is connected to the regulated current source ISS. [ 0071 ] The flip-flop PRS made of current-mode gates can be regulated in terms of speed by changing the current value of these gates . Lower current means slower operation, whereas higher current means faster operation. Current sources in the form of current mirrors allow to easy and simultaneous control of multiple current sources .

[ 0072 ] The invention can be applied and used in generation and priority detection of metastability phenomena, and particularly in generating truly random numbers and series in circuits resistant to side-channel attacks and changing ambient conditions.