FIELD OF INVENTION

The present invention relates to the field of communication technologies and in particular to the CDR (Clock and Data Recovery) circuit.

BACKGROUND OF THE INVENTION

As the data rates increase with the limited bandwidth of the I/O channel, inter-symbol interference and the co-channel interference dominate the BER (bit-error rate) of the communication link. Precise sampling instant in the data Ul (unit interval) needs to be determined for efficient recovery of the data with resultant jitter. Prevailing CDR architectures can be classified into two broad categories based on the recovery schemes as low bandwidth, large locking time loop based architectures and high bandwidth low locking time open-loop architectures.

The two important design parameters for the clock and data recovery circuit (CDR) are the Jitter Transfer function and the Jitter tolerance versus frequency for the CDR. Ideally the CDR circuit is desired to have a very low jitter transfer and generation characteristic and a very high jitter tolerance to the noise in the data stream. Various specifications place different requirements in terms of these parameters. Therefore there is need in art to achieve the desired performance of the CDR. OBJECTIVE OF THE INVENTION

An objective of the present invention is to achieve high jitter tolerance CDR with finite frequency offset between data and clock during data sampling.

SUMMARY OF THE INVENTION

An enhanced jitter tolerant programmable clock and data recovery circuit (CDR) comprises of the blind-oversampling CDR placed in a first order delay locked loop with the data. In the blind oversampling CDR, the output clock is a function of the two abounding edges for the current data-bit and previous "n" data edges. This entails a non-casual system as the occurrence of the succeeding edge of data for the current bit is unknown in prior to position the sampling clock. At the best average of all the preceding data crossovers is taken as the reference to place the sampling edge of the clock (PLL-based scheme). To ensure causality in the implementation of this scheme a calibrated delay is placed in the data path. The information on data crossovers is computed by the blind-oversampling circuit and the input data is delayed to coarsely match the computation of the crossovers over 1 Ul in the blind-oversampling circuit. The position of the clock phase approximately in the middle of the two abounding data crossovers for a given bit is computed in the blind-oversampling circuit. The delayed data is resampled by the clock phase determined by the blind- oversampling circuit to position it in the middle of the two data crossovers abounding the data-bit on average with a first order delay locked loop formed with the input data. The CDR tolerates a finite frequency offset without employing a separate loop.

The clock and data recovery method enhances the jitter tolerance of the CDR and also acquires lock for a burst mode of the data transfer with limited resolution.

BRIEF DESCRIPTION OF DRAWINGS

Figure 1 A depicts the Phase Locked Loop (PLL) based CDR circuit.

Figure 1 shows CDR depicting the oversampling data recovery and first-order track loop.

Figure 2 depicts block level diagram showing an embodiment of oversampling CDR architecture.

Figure 3 depicts frequency tolerance represented on the phase diagram by choosing a different phase every Ul.

Figure 4 depicts block level schematic for the four DFF's sampled by phased clocks. Figure 5 shows sampling and retiming in phase detect block Figure 6 shows the phase detection for the positive edges of the equi-distant clock phases Figure 7 depicts an embodiment of logic processing block

Figure 8 shows top-level design for the logic block

Figure 9 shows Sub-logic for individual phase selection.

Figure 10 depicts decision boundaries for the in-phase and quadrature clocks Figure 11 shows a case of long CID's for deriving the control bits.

Figure 12 shows simulated BER for different values of frequency error and jitter on clock with CID

Figure 13 shows the top-level design of the select block using digitally calibrated phase interpolators

Figure 14 shows different clock phases selected by their respective enable bits

Figure 15 shows the two outputs from operate block also showing the inter stage feedback for the operate block to generate the output clock.

Figure 16. showing the delay in the data path as quantized into the multiples of clock's phase shift. Figure 17 shows concept of operation of blind oversampling clock recovery.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention as embodied by a method for achieving higher jitter tolerance in a CDR circuit and the CDR circuit thereof, succinctly fulfils the above-mentioned need(s) in the art. The present invention has objective(s) arising as a result of the above-mentioned need(s), said objective(s) being enumerated below. In as much as the objective(s) of the present invention are enumerated, it will be obvious to a person skilled in the art that, the enumerated objective(s) are not exhaustive of the present invention in its entirety, and are enclosed solely for the purpose of illustration. Further, the present invention encloses within its scope and purview, any structural alternative(s) and/or any functional equivalent(s) even though, such structural alternative(s) and/or any functional equivalent(s) are not mentioned explicitly herein or elsewhere, in the present disclosure. The present invention therefore encompasses also, any improvisation(s)/modification(s) applied to the structural alternative(s)/functional alternative(s) within its scope and purview. The present invention may be embodied in other specific form(s) without departing from the spirit or essential attributes thereof.

Throughout this specification, the use of the word "comprise" and variations such as "comprises" and "comprising" may imply the inclusion of an element or elements not specifically recited. A CDR circuit comprises a over-sampling clock recovery block (101) which is in first order track loop delay in data, a Delayed Locked loop (DLL) (102) for the delay in clock and a Digital Signal Processing (DSP) (103) block for calibrating the delay of data for each unit interval, DLL formed with data with said DSP (103) block comprises a digital loop filter (121) and an encoder (122). Said DLL (102) comprises a delay chain (104), a first phase detector (105) and a loop filter

(106) . An external clock is fed to the delay chain (104), which produces the plurality of equally spaced clock phases, wherein said clock phases are in delay by the predetermined value from the DLL (102), which is in first order track loop with the first phase detector (105) and loop filter (106), wherein DLL (102) generates clock calibration codes (CC1) based on the accumulation factor of the loop filter (106) which is function of the abounding clock. Said plurality of equally spaced clock phases, in half-rate fed to the various blocks of the over- sampling clock recovery block (101).

Said over-sampling clock recovery block (101) comprises a sampler and re-aligner block

(107) , a logic block (108), a operate block (109), a voltage controlled delay line (VCDL) (110) and a Alexander type phase detector (!!PD) (111). A data is fed as input to the VCDL (110) and also to the sampler and re-aligner block (107), said sampler and re-aligner (107) block comprises a plurality of sampler and aligner (112) and a second phase detector (113), furthermore the sampler and re-aligner block (107) also receives the half-rate of the plurality of equally spaced clock phases from DLL (102) as input, wherein said plurality of sampler and aligner (112) comprises a dedicated sampler and aligner for the rising edge (112a) of the unit interval of the input data and a dedicated sampler and aligner for the falling edge (112b) of the unit interval of the input data, furthermore each of the plurality of the sampler and aligner (112) comprises a plurality of D Flip Flop (DFF).said plurality of sampler and aligner (112) samples the unit interval of the input data, multiple times, furthermore with respect to the falling or rising data edge of the unit interval the dedicated sampler and aligner (112a/112b) is chosen, said DFF in the plurality of sampler and aligner (112) samples the unit interval of the input data with respect to the each of the half-rate of the plurality of equally spaced clock phases, furthermore the sampler and aligner

(112) , aligns the sampled data with respect to the each the half-rate of the plurality of equally spaced clock phases, said sampled and aligned data is fed to the second phase detector

(113) , wherein said second phase detector (113) comprises a plurality of XOR gates, said second phase detector (113) co-relates the sampled and aligned data cyclically in-phase to determine the position of the data crossovers with respect to the each of the half rate of the plurality of equally spaced clock phases, the output of the second phase detector (113) is re- sampled and re-aligned to ensure that information is retained for at-least consecutive two unit interval, said retained information about sampled data for at-least consecutive two unit interval is fed to the logic block (108),

Said logic block (108) comprises a plurality logic unit (114), wherein said plurality of logic unit is dedicated for a rising data edge (114a) and also dedicated for a falling data edge (114b), wherein each of the plurality of logic unit (114a/114b) comprises of a plurality of sub-logic unit (115) and as much as a plurality of memory unit (116), wherein said sub-logic (115) unit comprises plurality of logic gates

Output from the sampler and re-aligner block (107) is fed as input along with the half-rate clock from the DLL (102) to the logic block (108), the logic block (108) replicates the logic for generating controls for the positive and negative edges for each of the half-rate of the plurality of equally spaced clock phases, the combination of plurality of logic gates ensures that control bits are generated every unit interval or with the occurrence of data crossovers, furthermore outputs of the logic unit (114a/114b) on the rising or falling edges are retimed to the respective complementary edge of the predetermined clock phase of the plurality of the half-rate of the clock phases (that is output for rising edge of the are retimed on the falling edge of the predetermined clock phase), said logic block (108) generates control bits for the selection of clock's phase for every Ul that is nearest to the center of the data bit, wherein said generated control bits controls the functioning of the operate block (109),

Said operate block (109) is interfaced with a digital filter (118), wherein operate block (109) comprises a plurality of select blocks (117) interfaced with a plurality of multiplexer (120), wherein a dedicated select block for the rising data edge (117a) and a dedicated select block for the falling data edge (117b), each of the plurality select blocks (117a/117b) comprises a plurality of phase interpolators (119) which is interfaced with the plurality of multiplexers (120), Output from logic block (108) is fed to the digital filter (118), wherein said digital filter processes the signals from the logic block and gives output as filtered signals with low jitter frequency, output from digital filter (118) along with the half-rate of the plurality of the clock phases is fed as input to the operate block (109), said plurality of phase interpolators (119) are configured to be equivocal for the input clock phases to give the output phase in middle of two input phases, said plurality of select blocks (117a/117b) in the operate block (108) using digitally calibrated plurality of phase interpolators (119) selects a clock phase after the occurrence of every data crossover with a resolution of 2* no, where no is the number of clock phases per Ul, the outputs from the plurality of select blocks (117a/117b) with the inter stage feedback generates the output clock, said output from each of the plurality of select blocks (117a/117b) are fed to the plurality of multiplexer (120) for recovering the clock for the rising and falling data edges sequentially, the recovered clock is the output of the operate block (109), the said output is fed to the !!PD (111)

Replica of the operate block (109) is placed in the data path with the control inputs tied to respective supply rails and fed the inputs tied to the delayed data signal from the output of the VCDL (110) to compensate for the propagation delay of the clock signal in the clock path by emulating the propagation delay of operate block (109), the delayed data is fed to the !!PD (111)

The !!PD (111) gives the output as the recovered data by recovering the data with respect to The recovered clock phases, said output is fed to the DSP block (103), Said DSP block (103) comprises a digital loop filter (121) and an encoder (122), the output data from the !!PD (111) is given as input to the digital loop filter (121), said digital loop filter

(121) process the data and forward the processed data to the encoder (122), said encoder

(122) keeps the count of all previous data cross-over and generate the data calibration codes (CC2) for the calibration of data delay base on the previous data cross-over. In method

VCDL in the data path, re-sample the delayed data with the selected clock to form a casual system. The recovered clock is aligned with data crossovers with limited resolution given as a function of the phase quantization of the unit interval. Clock recovery with finite error with respect to data crossovers the clock is aligned to centre of the data crossovers (left and right) on average with the first order delay locked loop with the incoming data. This ensures a minimum BER for given parameters defining the communication link.

In an example oversampling clock recovery block

A data bit is 4 times sampled (4*f _B ) by equidistant phases of the half rate clock separated by a time interval of 1/4 *UI. A Ul spans 0 - 180 degrees with respect to the half-rate clock frequency of h=2, that is a time period of this clock equals 2 Ul/data-bits. In fig. 3 depicts the phase jump/gain achieved by progressively selecting a new clock phase every Ul that has a minimum phase offset with respect to the current clock phase. The phase gain shown here is 45 degrees based on the phase quantization as designed in the system. The data is fed to the pair of sampler and aligner (112a and 112b) (set of 4 D flip-flops) each corresponding to the rising and falling edges of the half-rate blind clock. Fig. 4 depicts a set of 4 D flip-flops (DFF) sampled by the respective clock phases of the blind half-rate clock as a 4-bit memory block. The phases are marked as CLKO, CLK45, CLK90, CLK135 with positive edge of the clock as the active sampling edge and the respective outputs as "Qui", where "U/D" denotes the rising/falling edge samples and "i" denotes the relative clock phase.

The sampler and re-aligner block (107) also realigns the output of the pair of sampler and aligner (112a and 112b) by retiming on a single phase of the clock for correlation in the phase detector (see Fig. 1.15). Fig. 1.15 shows two set of paths based on the activity on the rising or falling edge of the clock phases. The figure shows the re-timing of the sampled data (shown in grey) for the rising/falling edges respectively (see Fig. 5). The retimed samples are then cyclically correlated to detect data crossovers in the second phase detector (113). The output of the sampler is fed to the second phase detector (113). The second phase detector (113) comprises of a bank of XOR gates that correlates the samples cyclically in phase to determine the position of data crossovers with respect to the clock phases Fig. 6.

The outputs of the second phase detector (113) (for rising and falling edges) are re-sampled to ensure that the information is retained for two consecutive clock periods. This enables the logic implementation with samples accumulating on every transition of the half-rate clock. Fig. 5 shows two sets of outputs Qius, Chus, C us, CUus and QIDS, Q2DS, Q3DS, Q DS for correlation of samples cyclically captured on rising and falling edges of the clock respectively. The method is to locate the position of two consecutive data crossovers abounding a data-bit by observing the samples over two consecutive Ul's. The outputs Qius and QIDS, for i = 1 ,2,3,4 form the inputs to the logic block (108). The logic block (108) generates control bits for the selection of clock's phase every Ul that is nearest to the center of the data bit by pure combinational processing of 12-bit output (from the sampling and retiming block Fig. 5) accumulated over 2UI. The processing of the information in logic block (108) as a function of the samples collected on successive clock edges is shown in Fig. 7. The figure shows each logic unit (114a and 114b) operates on the samples collected on opposite transitions for successive phases of the blind half-rate clock. The logic block (108) replicates the logic for generating controls for the positive and negative edges for the clock phases. Fig. 8 shows top-level design for the logic block (108) comprising of two logic units (114a and 114b) having inputs from the sampler and re-aligner block (107) (see Fig. 5). Fig. 9 shows the combinational logic implemented by standard logic gates in the plurality of sub-logic unit (115) for determining the phase of the sampling clock every Ul. Every Ul is quantized into 4 equal phase intervals (by the four different phases of the clock). This can be abstracted as two quantization intervals each around the two phases CLKO and CLK90 marked as REGION-1 and REGION-2 respectively (see Fig. 10). The logic block (108) generates controls for selecting a clock phase in middle of two adjacent clock phases say E(ij), where i, and j are two adjacent clock phases (see Fig. 9). For logic operations, the clock phases have the corresponding selection bits (active high) represented as CLKO == E(1); CLK45 == E(2); CLK90 == E(3); CLK135 == E(4). Logic for selecting the clock phase is defined by the following equations E(12) = (((Q.3DS ^Λ Q.2U) V (Q ₂ Ds V Q _3U )) V (Q _3DS ^Λ Qsu))

E(14) = (((QIDS ^Λ Q.2U) V (Q ₂ Ds V Qiu)) V (Q _2D s ^Λ Q ₂ u))

E(32) = (((Q _3DS ^Λ C U) V (G DS V Q _3U )) V (Q _4D s ^Λ C U))

E(34) = (((QIDS ^Λ Qiu) V (Qiu V Q _4U )) V (QIDS ^Λ C DS))

The combination of logic gates in the plurality of sub-logic unit (115) ensures that control bits are generated every Ul or with the occurrence of data crossovers. The outputs of the logic block (108) for the samples captured on the rising or falling edges are retimed to the respective complementary edge of the clock phase CLK135 (that is for rising edge captured samples are retimed on the falling edge of CLK135). The two logic units (114a and 114b) configured to generate outputs at every alternate edge of the clock 'CLK135'(see Fig. 7) . In case of consecutive identical digits (CID's), the plurality of sub logic unit (115) derives a null code (6b'00000) corresponding to the absence of data crossovers for samples captured on the rising or falling clock transitions per Ul. In this case the outputs of the logic block (108) are latched to the last control state taking in account the position of last crossover (see Fig. 11). The control state is only updated by the occurrence of an imminent crossover following CID's. The selection of sampling phase is then a function of total jitter on the data with respect to the present clock's phase. The clock's jitter is assumed to be independent of the jitter on the data (see Fig. 1.21). The new phase control is a function of new data crossover and the past control state of the logic block (108). Fig.9 highlights the plurality of memory block (116) that latches the previous output bit and compares it with the present output control bit. This scheme enhances the frequency tolerance in presence of jitter to give a low BER for the simulated model of the oversampling circuit for clock recovery (101) (Fig. 12). For computing the frequency tolerance with a given number of CID's the probability of error in recovering n ^th bit (d _n ) needs to be calculated in the presence of jitter on the data and clock (assuming Gaussian distribution for the random jitter). This amounts to finding the probability of the sampled data-bit other than d _n when sampled by the n ^th clock's edge (c _n ) It is possible that the right abounding data-edge (see Fig. 12) corresponding to d _n (e _n ) arrives before the corresponding sampling clock edge c _n or e _n -i arrives later than c _n , due to the jitter on received data or sampling clock resulting in error sampling. If fe is the data rate and fB ¹ = - δίβ is the clock's frequency, then e _n and c _n happen at t = η/ίβ and at t = (2*n-1)/ (2%) respectively. The probability of error after long CID's or a particular value of the random jitter (see Fig. 1.22) can be derived as probability of c _n occurring after to multiplied by the probability of en occurring before to assuming independence of the jitter on the clock and data edges. The probability of error can be written as

BEE- ^' PiA > t ) ¾ < t» ⁾

The outputs from the logic block (108) controls the functioning of operate block (109) to generate the recovered clock. The operate block (109) selects a clock phase every Ul based on the control inputs from logic block (108). The select block (117a and 117b) in the operate block (109) selects a clock phase after the occurrence of every data crossover with a resolution of 2* no, where no is the number of clock phases per Ul (4 in this case). Fig. 13 shows the top-level design of the select block (117a and 117b) using digitally calibrated phase interpolators (119). The phase interpolators (119) are configured to be equivocal for the input clock phases to give the output phase in middle of two input phases (for e.g. an active E12 selects the phase in-between CLK0 and CLK45). The 6-bit logic output for the rising/falling edge captured samples provide the control for selection of the phase corresponding to the output index for the logic block (108) (Fig. 14). Fig. 14 shows the control/enable bits for the respective clock phases. The index for the control bits specify the clock's phase for example Ei specifies the control bit for CLK0 and the control-bit E12 corresponds to the phase in-between CLKO and CLK45. Note that the control bits (E,, for i=1 , 2, 3, 4) for clock phases from the DLL (102) does not exists. The clock phases from the DLL (102) enter the operate block (109) which uses equivocal phase interpolators (119) for generating the clock phases midway between the given phases. Offset bits (E ₀ ffset) offset the output phase by a +/- 22.5° in the phase interpolators (119). The phase interpolators (119) is quantized to give three output phases for input clock phases LCLK and RCLK and the input selection bits t offset,

Fig. 15 shows the two outputs from select block (117a and 117b) (CLKOP1ANDCLKOP2) also showing the inter stage feedback for the select block (117a and 117b) to generate the output clock CLKOUT . The outputs of the respective select blocks (117a and 117b) are fed to a multiplexer (120) selecting the clock for the rising and falling edges sequentially.

A replica operate block (109) is placed in the data path with the control inputs tied to respective supply rails and fed the inputs tied to the delayed data signal from the output of the VCDL (110). This is done to compensate for the propagation delay of the clock signal in the clock path by emulating the propagation delay of operate block (109). Fig. 16 shows the timing diagram for calibration of the VCDL (110) in the data path. The figure epitomizes the operation of the CDR on time axis as a function of phases of the blind half-rate clock. Fig. 16 shows 4 sampling phases of the clock (CLKO, CLK45, CLK90 and CLK135) and the processing sequence (on the time-scale) of the data-samples collected in the first and second Ul. Note that the sampler and re-aligner block (107) and the logic block (108) use first four phases (CLKO, CLK45, CLK90, CLK135) of the clock and the select block (117) uses CLK180, CLK225, CLK270, CLK315 as inputs. This satisfies the timing constraint for the error-free operation of operate block (109) and equalizes the loading on the clock phases. The output of logic block (108) is retimed on a single clock phase (CLK135) and the operate block (109) uses all clock phases with a minimum offset of + 45° with respect to CLK135.

The output from the over-sampling clock recovery block (101) is given as input to the DSP (103) to generate the CC2, wherein said CC2 calibrates the delay of the data in the VCDL (110).

REFERENCE NUMERALS

101 - over-sampling clock recovery block

102 - Delayed lock loop (DLL)

103 - Digital Signal processing (DSP) block

104 - Delay chain

105 - first phase detector

106 - loop filter

107 - sampler and re-aligner block

108 - logic block

109 - operate block

110 - voltage controlled delay line (VCDL)

111 - Alexander type phase detector (!!PD)

112 - sampler and aligner

112a - dedicated sampler and aligner for rising data edge

112b - dedicated sampler and aligner for falling data edge

113 - second phase detector

114 - logic unit

114a - dedicated logic unit for rising data edge

114b - dedicated logic unit for falling data edge

115 - sub-logic unit

116 - memory unit

117 - select block

117a - dedicated select block for rising data edge

117b - dedicated select block for falling data edge

118 - digital filter

119 - phase interpolator

120 - multiplexer

121 - digital loop filter

122 - encoder

CC1 - clock calibration code

CC2 - data calibration code