METHOD FOR AMPLIFIER LOAD CURRENT CANCELLATION IN A CURRENT INTEGRATOR AND CURRENT INTEGRATOR WITH AMPLIFIER LOAD CURRENT CANCELLATION

The present invention relates to the field of current

integrators with switched-capacitor digital-to-analog

converter .

The circuit diagram shown in Figure 6 depicts a basic circuit topology of a typical integration stage used in a digital-to- analog converter (DAC) . Current is integrated on an

integration capacitor Ci _nt by enforcing a virtual ground potential v _n on the input current Ii _n . The virtual ground potential v _n is the quotient of the output current I _out and the transconductance g _m : v _n = I _out /g _m .

As the increasing current on the integration capacitor Ci _nt results in an increasing output voltage V _out , the circuit is almost always used in feedback, such as in delta-sigma converters. Feedback can be generated by a current source or a switched-capacitor digital-to-analog converter (SC DAC) , which injects current into the node of the virtual ground potential to subtract charge from the integration capacitor, thus keeping the output voltage V _out in the allowed range.

In a switched-capacitor digital-to-analog converter, charge packages of size Q = C (V _DA C - v _n ) are injected, where C is the capacitance of the integration capacitor Ci _nt and V _DA C is a supply voltage of the digital-to-analog converter. Hence the virtual ground potential v _n directly affects the DAC charge. As the capacitance of the load capacitor C _L can be considered linear, the output current I _out is also linearly related to the input current Ii _n , thereby making the virtual ground potential v _n depend on the input signal. This signal

dependency causes nonlinearity which is inacceptable in high accuracy applications.

To tackle this problem, the transconductance g _m may be increased in order to reduce the virtual ground potential v _n , but this comes at the expense of higher power consumption. Alternatively, digital calibration can be employed, but this method requires estimation of a calibration constant for each device, which may be difficult to achieve with sufficient accuracy to comply with very high linearity requirements.

A more practical solution is to minimize the output load current of the operational transconductance amplifier (OTA) . Such a technique has been proposed for voltage input delta- sigma converters wherein virtual ground spikes during

feedback are minimized by injecting the DAC signal and the estimated input signal charge at the output. The effective input current is estimated by means of a feed-forward

transconductor g _mff , as in the circuit shown in Figure 7.

However, the feed-forward transconductance g _mff will not match the resistor R accurately over process, temperature and input signal variations, and the elimination of deviations of the virtual ground potential v _n may not be sufficiently precise for high-linearity applications.

Known solutions focus at reducing the dynamic deviations Av _n , _dyn of the virtual ground potential v _n at the beginning of the DAC pulse in voltage input integration stages (Figure 8) . But for a highly linear SC DAC, the static deviation Av _n , _st at of the virtual ground potential v _n at the end of the DAC pulse is important, because it determines the accuracy of the charge transfer. The virtual ground potential v _n should be equal to the ground potential at the end of the DAC pulse.

Furthermore, the known solutions assume that the major output current of the operational transconductance amplifier flows into the integration capacitor Ci _nt · If the capacitance of the load capacitor C _L is a multiple of the capacitance of the integration capacitor Ci _nt# the load current of the

operational transconductance amplifier is accordingly higher. In particular if different types of capacitors C _L and Ci _nt are employed, process tolerances and temperature variations may render the minimization of the load current inefficient.

It is an object of the present invention to disclose a practical way of reducing nonlinearity in current

integrators, in order to make process and temperature

dependent calibration redundant.

This object is achieved with the method according to claim 1 and with the current integrator according to claim 8.

Variants and embodiments derive from the dependent claims.

The definitions as described above also apply to the

following description unless stated otherwise.

The method for amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing

resistor, thus eliminating a dependence of the output current on the input current.

In a variant of the method, the voltage drop over the sensing resistor is integrated, and the integrated voltage drop is converted into the cancellation current. A switched capacitor integrator may be provided to integrate the voltage drop. The cancellation current may particularly be injected to the output current after the output current passes the sensing resistor .

In a further variant of the method, the voltage drop over the sensing resistor is sampled on a capacitor, and the sampled voltage drop is converted into the cancellation current. This conversion may especially be effected by means of a further operational transconductance amplifier. The cancellation current may particularly be injected to the output current before the output current passes the sensing resistor.

The current integrator comprises an operational

transconductance amplifier provided with an integration capacitor for current integration, a sensing resistor

connected to an output of the operational transconductance amplifier, a conversion circuit configured for converting a voltage drop over the sensing resistor to a cancellation current, and

a connection between an output of the conversion circuit and a node located immediately before or immediately after the sensing resistor. In an embodiment of the current integrator, the conversion circuit comprises a further integrator configured to

integrate the voltage drop over the sensing resistor. The further integrator may especially be a switched capacitor integrator .

A further embodiment of the current integrator comprises a further operational transconductance amplifier of the conversion circuit. The further operational transconductance amplifier is configured to convert an output of the further integrator into the cancellation current.

In a further embodiment of the current integrator, the sensing resistor is arranged between the operational transconductance amplifier and an output node, and an output of the further operational transconductance amplifier is connected to the output node.

In a further embodiment of the current integrator, the conversion circuit is configured to sample the voltage drop over the sensing resistor on a capacitor. In particular, a further operational transconductance amplifier may be employed to convert the sampled voltage drop into the cancellation current. An output of the further operational transconductance amplifier may expecially be connected to a node between the operational transconductance amplifier and the sensing resistor.

The following is a detailed description of examples of the method and the current integrator in conjunction with the appended figures. Figure 1 shows diagrams illustrating a load current

cancellation method.

Figure 2 shows diagrams illustrating a further load current cancellation method.

Figure 3 shows a circuit diagram for an implementation of the further load current cancellation method.

Figure 4 shows a circuit diagram of a current domain

incremental two-step analog-to-digital converter using the load current cancellation circuit.

Figure 5 is a timing diagram for the circuit of Figure 4.

Figure 6 shows a circuit diagram of a basic integration stage used in delta-sigma converters.

Figure 7 shows a circuit diagram of an assisted operational amplifier technique.

Figure 8 shows the supply voltage V _DA C and the deviations of the virtual ground potential v _n from the ground potential gnd as functions of time t.

Figure 1 shows diagrams illustrating a load current

cancellation method. The operational transconductance

amplifier has a transconductance g _m . An integration capacitor Ci _nt is provided for current integration. A sensing resistor R _Sense is provided to sense the output current I _out in order to obtain a linear estimate of the output current I _out · The sensing resistor R _sense is sized for a voltage drop of a fraction of the available output swing of the operational transconductance amplifier in order not do degrade the performance of the operational transconductance amplifier.

The voltage drop over the sensing resistor R _se nse is buffered and integrated, in particular with a switched capacitor integrator, for instance.

The integrator output is converted into a current which is injected at the output via a further operational

transconductance amplifier, which has a transconductance g _m 2. In turn the output current of the operational

transconductance amplifier will decrease, which reduces the voltage drop over the sensing resistor R _senS e · Thus a feedback loop is formed, which drives the voltage drop over the sensing resistor R _se nse (i. e., the load current of the

operational transconductance amplifier) to zero. This feedback loop is nested in the feedback loop of the

operational transconductance amplifier and requires low loop gain to guarantee stability.

Figure 2 shows diagrams illustrating a further load current cancellation method, which does not use feedback. The voltage drop over the sensing resistor R _se nse is buffered and sampled, in particular on a capacitor, for instance. For this purpose two separate capacitors may be provided, which are

alternatingly switched by a first clock signal clki and a second clock signal clk2 synchronized with the DAC clock signal clk _DAC , as shown in Figure 2. The sampled voltage is converted to a cancellation current I _out , _cancel/ which cancels the load current at the output of the operational

transconductance amplifier.

In the circuit according to Figure 2, there is no feedback loop to pose stability and settling requirements, because the operational transconductance amplifier will always adjust its output current I _ou t to match the required load current Ii _oa d in combination with the injected cancellation current I _ou t, cancel : lout lout, cancel t lload

Hence the voltage drop over the sensing resistor R _se nse is constant and independent of the cancellation current

lout, cancel· The cancellation current I _ou t, cancel is injected based on the measured output current I _out from the previous clock cycle. This cancellation scheme is therefore efficient as long as the time constant of the input signal is larger than the period of the DAC clock signal clk _DAC . This is typically the case in oversampled delta-sigma converters. This

assumption is valid especially when low-frequency linearity is a concern.

An example of a detailed circuit implementation of the further load current cancellation method is depicted in

Figure 3. The voltage at the sensing resistor R _se nse may be differentially sampled to eliminate systematic charge

injection errors. A connection of both capacitors during switch transitions can be avoided by a non-overlapping sample clock. Moreover, switching according to the first clock signal clki and the second clock signal clk2 is performed after the DAC settling finishes. A linear transconductor is employed to convert the sampled voltage at the sensing resistor R _senS e to the cancellation current I _out, cancel = I _OUI' Q _R , where Q _R is the quotient of the electrical resistances of the sensing resistor R _se nse and the resistor R.

The achieved cancellation is essentially insensitive to process tolerances and temperature variations, since it only depends on the quotient Q _R , and an exact cancellation by an accurate match of the electrical resistances of the sensing resistor R _se nse and the resistor R is comparatively easily obtained. The linear transconductor employs local feedback to achieve linearity and thus is subjected to the same settling constraint as the main integrator itself.

However, owing to the absence of a large load capacitance in the local feedback loop, the settling requirement can be achieved at much lower power consumption than for the main integrator. Besides, noise from the buffer and transconductor is injected at the integrator output so that it is highly supressed by the OTA open loop gain. Hence, the power and noise penalty of the load current cancellation scheme is low.

Figure 4 shows a circuit diagram of a current domain

incremental two-step analog-to-digital converter. In this circuit the residue of the first analog-to-digital converter is converted by a second stage analog-to-digital converter. The first stage is implemented as current controlled

oscillator (CCO) . The integrator output is compared to a reference voltage V _ref , and the comparator output is

synchronized to the clock signal elk. The synchronized comparator output triggers the DAC feedback pulses. DAC feedback is realized by a precharged capacitor that is discharged into the virtual ground node (SC DAC) . The total number of feedback pulses n _count during one full integration period Ti _nt provides the course analog-to-digital conversion value .

The first stage can work as stand-alone or be combined with a fine conversion result by digitization of the output residue V _residue of the CCO in order to increase resolution. As the two-stage concept requires a large sampling capacitor that might not correlate to the integration capacitor Ci _nt in terms of process, voltage and temperature variation (PVT) , using the output cancellation technique described above is

particularly powerful because it is inherently PVT robust.

Figure 5 is a timing diagram for the circuit of Figure 4. Figure 5 shows the elk signal elk, the sample and reset signal pulses, the pulsed voltage V _puise , and the integrated output voltage V _{out ±nt} as functions of the time t.

An offset in the buffer and linear transconductor translate to increased offset at the OTA input. This does not affect linearity but gives rise to a constant DAC offset error. This is not a drawback, because the operational transconductance amplifier itself exhibits offset, and hence the DAC offset must anyway be calibrated in applications with high gain accuracy requirements.

With the described method the output current is precisely measured and converted into a precise cancellation current. Linearity is thus guaranteed, as opposed to conventional calibration assisted solutions. This method has the advantage that it takes account of the static deviation Av _n , _st at of the virtual ground potential v _n at the end of the DAC pulse. The described method accurately eliminates the static error both for voltage and current domain topologies. List of reference numerals

Cint integration capacitor

C _L load capacitor

elk clock signal

cl _DA c DAC clock signal

clki first clock signal

clk ₂ second clock signal

g _m transconductance

g _m2 further transconductance

g _mff feed-forward transconductance

gnd ground potential

I in input current

I load load current

I out output current

I out , cancel cancellation current

recount total number of feedback pulses

R resistor

Rsense sensing resistor

VDAC supply voltage

V _n virtual ground potential

Dn _h , dyn dynamic deviation of the virtual ground potential Dn _h , _s tat static deviation of the virtual ground potential Vout_int integrated output voltage

Impulse pulsed voltage

Vref reference voltage