FOR DETECTING IMPENDING OVERFLOW

AND/OR UNDERRUN OF ELASTICITY BUFFER

BACKGROUND OF THE INVENTION

This invention is related to computer networks, and more particularly, to computer networks that transfer frames of data through repeater nodes using elasticity buffers, and in which each node connected to the network is operated by an independent clock. RELATED APPLICATION

This application is a continuation-in-part of U.S. Patent Application Serial No. 07/187,208, entitled "Method and Apparatus for Nodes in Network to Avoid Shrinkage of an Interframe Gap," filed April 28, 1988 by Charles W. Kaufman, Mark F. Kempf, and Jerry D. Hutchison, and which is assigned to the assignee of this application. BACKGROUND OF THE INVENTION

In the field of data communications, quantities of data known as "frames" are often transmitted from one node (station) to another through a network of nodes that operate using their own independent clocks. Use of independent clocks in the nodes requires a system for ensuring that data corruption will not occur when frames are transmitted from a source node to a destination node through a number of repeat¬ er nodes. One method commonly employed for preventing data corruption in such networks is the use of an elasticity buffer at each node.

An elasticity buffer is a first-in first-out stor¬ age device including a number of single or multibit storage elements. In the elasticity buffer, data enters and exits at different rates corresponding to the different frequency of the clock used in the upstream transmitting node compared with the local clock frequency used in the receiving node. Elasticity buffers are required even though data transfer rates are nominally the same, because independent clocks in separate nodes will differ in frequency within some known tolerance.

An elasticity buffer :s used when the incoming data rate may vary from the outgoing data rate. The independent

clocks in different nodes are asynchronous, and at some point, data from an upstream node (the sending station) must be synchronized to the local clock in the repeater node receiving the data. Typically, incoming data is received synchronously with a transmit clock signal of the upstream node. The transmit clock signal may be sent to the repeater node on a dedicated clock line, or the transmit clock signal may be recovered by the repeater node from incoming data using a clock recovery device.

After data is received by the repeater node, some implementations provide that the data is first synchronized to the local clock aid then written into the storage elements of the elasticity buffer. In these systems, data is written into and read from the storage elements using the same local clock, and the buffer read/write operations are therefore synchronous.

In an elasticity buffer with synchronous read/write operations, each data unit (e.g., a byte) transferred through the elasticity buffer must first be pre-synchronized when the data unit is received by the repeater node. For synchronous elasticity buffers, however, metastability is a significant problem and may result in data corruption.

Metastability occurs when adequate setup and hold times for input data are not provided for a logic element (e.g., a flip-flop) that is latching in the data. In logic elements used for synchronization, the variation in clock speeds makes the time of arrival of each data unit uncertain, thereby causing errors when input data is sampled during a period of instability. Although failure rates may be reduced using sophisticated designs and multistage synchronizers, there is a probability of data corruption due to me¬ tastability each and every time logic elements performing the synchronization sample the signal levels on input data lines. Problems with metastability become more critical in nodes in which clock speeds are designed to approach the limits of existing device technology, because the probability of error increases as the speed at which the logic elements sample the

input data lines increases. In order to reduce the probabil¬ ity of data corruption, it is therefore desirable to minimize the frequency at which samples of input data are taken by logic elements performing the synchronization function.

Data corruption resulting from metastability is re¬ duced when an asynchronous elasticity buffer is used in the repeater node instead of a synchronous buffer. In the asynchronous elasticity buffer, data is written into storage elements in synchronism with the transmit clock signal, and data is read from the storage elements in synchronism with the local clock signal. Thus, the read and write operations for this elasticity buffer are totally asynchronous. As a result, there is no need to provide for sampling of each and every input data unit by a synchronizer logic element before it is written into a storage element. In repeater nodes utilizing asynchronous elasticity buffers, input data can be synchronized infrequently, e.g., once during each period when an entire frame of data is transmitted to the repeater node. Typically, input data is synchronized by the repeater node at the start of receipt of each frame of data from the upstream node.

Data is stored in an elasticity buffer as it arrives from an upstream node, and is read from the buffer for transmission to a downstream node at a rate determined by the local clock in the node. If the local clock for the re¬ peater node is slower than the transmit clock of the upstream node, the buffer will become more and more full as the data in a frame is transmitted through the node. If the local clock is faster than the transmit clock of the upstream node, the buffer gradually empties of all data.

The elasticity buffer in a repeater node between a source node and a destination node must therefore include enough storage elements to ensure it will not become full before the last data unit in a frame has been transmitted to a downstream node. If the buffer fills before the repeater node has transmitted the last data unit o the downstream node, the buffer cannot store additional data bemo

transmitted from an upstream node without corrupting previ¬ ously received data that has not yet been transmitted to the downstream node. When data is written into a storage element that has previously been written but has not yet been read, a write overflow condition exists.

An elasticity buffer in a repeater node between a source node and a destination node must also prevent a stor¬ age element from being simultaneously written and read, or from being read before it is written. A read underrun condi¬ tion exists when data is read from a storage element that has previously been read but has not yet been written. However, data corruption actually occurs before the read underrun whenever a storage element is read too soon after data is written into the storage element. Valid data cannot be read from a storage element at the same instant data is stored into the storage element. This is due to the fact that logic elements in an elasticity buffer, including the storage ele¬ ments, have propagation delays and setup and hold times.

Therefore, to minimize the probability of data cor¬ ruption due to a read underrun condition, a minimum delay is provided before reading of a storage element in which the first data unit in a frame has been written. Without such initialization (also referred to as resetting or recentering) of the elasticity buffer, a repeater node with a relatively fast clock empties its elasticity buffer and attempts to transmit data to the downstream node before the data has been received from the upstream node. Typically, the elasticity buffer is initialized at least once during transmission of every frame, usually at the start of receipt of each frame of data from the upstream node and/or after detecting that a write overflow or read underrun is impending.

In order to prevent any unacknowledged data corrup¬ tion due to write overflow or read underrun conditions, the repeater node detects whether write overflow and/or read underrun conditions are impending. Each storage element in the elasticity buffer has a unique address. Therefore, detection of overflows/underruns can be accoir.Diished bv

monitoring the write address and the read address. When the write address and read address pass each other in either direction, an overflow/underrun condition has occurred.

In nodes utilizing synchronous elasticity buffers, detecting when the write address and read address pass each other is easily accomplished because read/write operations are synchronous. In contrast, detecting an impending over- flow/underrun condition is much more difficult using asynchronous elasticity buffers because the selection of the write address Is not synchronous with the selection of the read address.

However, in choosing between synchronous and asynchronous elasticity buffers, it is important to recognize that overflow/underrun conditions do not occur in normal cir¬ cumstances. Therefore, it is better to minimize the proba¬ bility of data corruption due to metastability, which occurs even under normal conditions. For this reason, it is often preferable to use an asynchronous elasticity buffer, which will generate fewer data errors, provided a method of over- flow/underrun detection can be used that is effective and efficient.

Another decision involved in design of an elastic¬ ity buffer is whether to use a serial elasticity buffer or a parallel elasticity buffer. Although data is transferred between nodes in the network in serial format, it is often necessary to design the elasticity buffer to receive and transmit data in parallel format because available technology cannot operate at the higher speeds required for serial data transfer.

In some implementations of serial asynchronous elasticity buffers, overflow/underrun detection requires storing a flag for each memory location. The flag indicates whether a read or a write operation was the most recently performed operation at that location. Potential over- flows/underruns are detected ^** nenever a read attempt is made to a location at a time when the flag for the location that is next to be read indicates a read was most recently

performed, and whenever a write attempt is made to a location prior to completion of a read on the next location. Thus, overflow/underrun detection occurs whenever the read address and the write address point to storage elements that are within one location of each other.

In other implementations of serial asynchronous elasticity buffers, overflow/underrun detection requires mon¬ itoring of write select and read select lines corresponding to each data register in an elasticity buffer. An error sig¬ nal is asserted whenever the write select and read select lines corresponding to two contiguous data registers are enabled. Thus, overflow/underrun detection occurs whenever the read pointer and the write pointer select data registers that are within one location of each other.

The designs used for overflow/underrun detection in serial asynchronous elasticity buffers do not necessarily, however, provide for efficient overflow and/or underrun detection in parallel asynchronous elasticity buffers. These designs require a relatively large elasticity buffer, much of whici is unused, if applied to parallel elasticity buffers.

In the serial designs, overflow/underrun detection occurs if adjacent locations are selected for reading and writing at any time. In parallel buffers, a multibit clock signal has a period corresponding to the time between trans¬ fer of each data unit. Thus, the designs described above would detect overflow/underrun for a parallel elasticity buffer even though pointers for the write and read addresses are between one and two multibit clock signal periods apart.

However, underruns and overflows do not actually occur until shortly before the write and read addresses are being simultaneously selected. Therefore, an impending over¬ flow and/or underrun condition can be detected without risk of data corruption even when pointers for the write and read addresses are less than one multibit clock signal period apart. By providing a parallel buffer design in which over- flow/underrun detection occurs later than in the serial designs, the elasticity buffer itself can be made smaller and

simpler. In contrast, if the serial design is used for a parallel elasticity buffer, the buffer must be capable of storing at least one additional multibit data unit.

Furthermore, in a parallel buffer design having later overflow/underrun detection, the latency time of the buffer is reduced by making more of the buffer usable. By allowing pointers for the write and read addresses to be less than one multibit clock signal period apart, tolerances for the independent clocks in the nodes can be larger because more clock slippage is required before the buffer detects that an overflow and/or underrun condition is impending.

The principles discussed above apply to various types of wide and local area networks, including any packet data network which connects many repeater nodes that involves point-to-point clocking. Examples include nodes connected to a token ring network or to an Ethernet network connected with multiple repeaters.

A ring network consists of a set of nodes (sta¬ tions) logically connected as a serial string of nodes and transmission media to form a closed loop. Information is transmitted sequentially, as a stream of suitably encoded symbols, from one active node to the next. Each node gener¬ ally regenerates and repeats each symbol and serves as the means for attaching one or more devices to the network for the purpose of communicating with other devices the net¬ work.

A network of particular applicability is the fiber distributed data interface (FDDI), which is a proposed Ameri¬ can National Standard for a 100 megabit per second token ring using an optical fiber medium. The characteristics of FDDI networks are described in detail by Floyd E. Ross in "FDDI—A Tutorial," IEEE Communications Magazine, Vol. 24, No. 5, pp. 10-17 (May 1986), which is herein incorporated by refer¬ ence.

Information is transmitted on an FDDI ring network in frames using a four of five group code, with each five-bit code group being called a symbol. Of the thirty-two member

symbol set, sixteen are data symbols each representing four bits of ordered binary data, three are used for starting and ending delimiters, two are used as control indicators, and three are used for line-state signaling recognized by physi¬ cal layer hardware. Each byte corresponds to two symbols or ten bits. (The term multibit data unit is used throughout the specification as a convenient way to refer to any unit of data exceeding one bit in length; the functioning of the invention is not limited to any particular number of bits in the data unit, and such units of data as symbols and bytes are included. )

The data transmission rate is 100 megabits per sec¬ ond for FDDI. A 125 megabaud transmission rate is required because of the use of a four-of-five code on the optical fiber medium. The nature of the clocking limits data frames to a maximum length of 4,500 bytes (i.e., 9,000 symbols or 45,000 bits). An FDDI network consists of a theoretically unlimited number of connected nodes.

In FDDI networks, every transmission of a frame is preceded by a preamble field, which consists of idle line- state bytes (symbols). In FDDI, an idle line-state symbol corresponds to the five-bit code group 11111. At the begin¬ ning of the frame, the preamble field of idle bytes is fol¬ lowed by a starting delimiter field, which consists of a two-symbol sequence JK that is uniquely recognizable indepen¬ dent of previously established symbol boundaries. The starting delimiter field establishes the symbol boundaries for the content that follows. The five-bit code group corre¬ sponding to the symbol J is 11000, and the code group corre¬ sponding to the symbol K is 10001.

For FDDI, the nominal clock rate is 125 megahertz but a frequency tolerance of plus or minus .005% is allowed. The maximum frame size is 4,500 bytes. Given these con¬ straints, it is readily understood that passage of a single frame may result in the elasticity buffer in a repeater node filling or emptying at the rate of 4.5 bits per frame because of the maximum possible difference in clock frequencies in consecutive nodes ir. the network.

As has been described previously, the elasticity buffer in each node in a network compensates for any differ¬ ences in rates of the clocks for consecutive nodes in the network. When initialization of the elasticity buffer occurs before a subsequent frame is repeated by a node, the node will either i.isert or delete bytes from the total number of bytes it transmits to the downstream node, depending on whether the clock in the upstream node is slower or faster than the local clock for the node. By providing a preamble before each frame including at least a minimum number of idle bytes, the elasticity buffer can be initialized without any loss of data by only allowing addition or deletion of idle bytes in the preamble separating every pair of frames.

Therefore, in order to prevent allowable clock fre¬ quency differences from causing the elasticity buffer in a node from completely filling or emptying, the repeater node initializes its elasticity buffer by either expanding or shrinking the size of the preamble for the subsequent frame. Thus, one idle byte may be inserted in a preamble by a fast repeater node when it initializes to prevent its elasticity buffer from emptying, while one idle byte may be deleted by a slow repeater node when it initializes its elasticity buffer in order to prevent it from filling.

The FDDI network has a maximum frame size of 4,500 bytes and a clock tolerance of plus or minus .005%, so that a node will have to add or delete no more than 4.5 bits if it initializes its elasticity buffer following transmission of a frame. Therefore, additional bits of storage must be provid¬ ed in the elasticity buffer to accomodate for differences in data transfer rates. Although a slippage of 4.5 bits re¬ flects the maximum clock frequency differences from the nomi¬ nal frequency for all stations in the network, this does not prevent the relative position of the input and output point¬ ers from varying outside a range of 4.5 bits. Nodes do not ac i or delete fractions of bits from frames repeated to down¬ stream nodes because of the technical complexity and the resulting addition to the jitter seer, at the downstream node

due to a frequency shift for the duration of one bit. In¬ stead, the node rounds the number of bits it adds or del .tes to the nearest whole bit, and these roundoff errors can accu¬ mulate along the network. Furthermore, standards for nodes connected to a network such as FDDI do not specify a maximum roundoff error, and designers therefore plan implementations of nodes that round to the nearest byte (ten bits) or symbol (five bits). This increases the size of the roundoff errors.

An elasticity buffer is therefore required which reduces the number of data errors that will occur due to me¬ tastability but which will also detect impending overflow and/or ur.derrun conditions in an effective and efficient man¬ ner. Furthermore, the buffer must be practical for use in nodes coupled to any of a variety of data communication net¬ works.

Thus, there is a need for a method and apparatus for detecting impending overflow and/or underrun of a paral¬ lel asynchronous elasticity buffer. SUMMARY OF THE INVENTION

It is an object of the present invention to over¬ come certain problems and disadvantages of the prior art relating to metastability or to detection of impending over¬ flow and/or underrun of an elasticity buffer. It is there¬ fore desirable to provide a method and apparatus for detecting impending overflow and/or underrun using a parallel asynchronous elasticity buffer.

Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advan¬ tages of the invention may be realized and attained by means of the instrumentalities and combinations particularly point¬ ed out in the appended claims.

To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a parallel asynchronous elasticity buffer is provided in a repeater node for transferring data in a data

E SHEET

communication system. The data communication system includes a number of nodes coupled in a network for transferring frames of data from a source node to a destination node through the repeater node. The repeater node receives a num¬ ber of bits of data in a frame from an upstream node and transmits the data to a downstream node. Each node in the network transmits data in synchronism with an independent clock.

The elasticity buffer includes receiving means for providing in parallel format, in response to a transmit multibit clock signal that is in synchronism with an indepen¬ dent clock of the upstream node, a multibit data unit re¬ ceived from the upstream node. Storage means is provided and includes a fixed number of multibit storage elements, coupled to the receiving means, for storing the multibit data unit in parallel format in one of the storage elements, wherein each storage element has a unique address. Transmitting means is coupled to the storage means for outputting in parallel format, in response to a local multibit clock signal that is in synchronism with the independent clock of the repeater node, one of the multibit data units stored in the storage means. The buffer includes write pointer means, coupled to the storage means, for selecting as a write address the address of a storage element to store the next multibit data unit provided by the receiving means; and read pointer means, coupled to the storage means, for selecting as a read address the address of a storage element to provide the next multibit data unit output by the transmitting means, wherein each multibit data unit is output in first-in, first-out order. Initialization means is provided for initializing the elas¬ ticity buffer to prevent simultaneous selection of the same address as a read address and a write address, wherein in re¬ sponse to initialization, a write address is selected as a read address after a predetermined delay. The buffer also includes detection means for detecting whether an error con¬ dition corresponding to a write overflow or read underrun of a storage element is impending by determining whether the

same address is selected as the write address and as the read address during an overlap time period having a duration equal to a threshold time period.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one preferred embodiment of the invention, and, together with the description, serve to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram of a repeater node.

Figure 2 is a schematic diagram of a framer.

Figures 3A and 3B are schematic diagrams of storage circuitry.

Figure 4 is a schematic diagram of an input point¬ er.

Figure 5 is a schematic diagram of an output point¬ er.

Figure 6 is a schematic diagram of an input con¬ troller.

Figure 7 is a schematic diagram of a synchronizer.

Figure 8 is a schematic diagram of idle detection circuitry.

Figure 9 is a schematic diagram of an output idle counter.

Figure 10 is a schematic diagram of a reset state machine.

Figure 11 is a state diagram for a reset state ma¬ chine.

Figure 12 is a schematic diagram of over- flow/underrun detection circuitry.

Figure 13 is a schematic diagram of clock generator circuitry.

Figure 14 is an error detection timing chart.

Figure 15 is a write pointer timing chart.

Figure 16 is a read pointer timing chart.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the pre¬ ferred embodiments of the invention, examples of which are illustrated in the accompanying drawings.

A preferred embodiment of the repeater node is shown in Figure 1 and is represented generally by the numeral 10. The repeater node is provided in a data communication system, which includes a number of nodes coupled in a network for transferring frames of data from a source node to a des¬ tination node through the repeater node. The repeater node receives a number of bits of data in a frame from an upstream node and transmits the number of bits of data in the frame to a downstream node. Each node in the network transmits data in serial format in synchronism with its own independent clock.

In accordance with the invention, the repeater node includes a parallel asychronous elasticity buffer. The buffer is represented generally by the numeral 12 in Figure 1.

Repeater node 10 may include means for providing a transmit multibit clock signal that is in synchronism with the independent clock of the upstream node, and means for providing a local multibit clock signal that is in synchro¬ nism with the independent clock of repeater node 10. In a preferred embodiment of node 10, a transmit byte clock signal (TBYTECLK) corresponds to the transmit multibit clock signal, and a local byte clock signal (LBYTECLK) corresponds to the local multibit clock signal. Preferably, the transmit byte clock signal and local byte signal are provided by clock gen¬ erator circuitry 14, shown in Figure 1.

As shown in the embodiment of Figure 1, parallel asynchronous elasticity buffer 12 is provided with the trans¬ mit byte clock signal and the local byte clock signal by clock generator circuitry 14. A local oscillator circuit (not shown) in repeater node 10 generates a 12.5 megahertz TTL-compatible signal corresponding to a byte clock signal (BYTC K) and a 25 megahertz TTL-compatible signal

-14-

corresponding to a symbol clock signal (SYMCLK) as inputs to clock generator circuitry 14. A clock and data conversion chip (not shown) in repeater node 10 provides a 12.5 megahertz TTL-compatible signal corresponding to a recovered byte clock signal (RBCLK) as another input to clock generator circuitry 14.

In a preferred embodiment, repeater node 10 is cou¬ pled to a token ring network, such as a network in which data communication is performed in accordance with the FDDI proto¬ col. As embodied herein, repeater node 10 receives and transmits data in accordance with the FDDI protocol.

In the FDDI protocol, the period of the local byte clock signal for each node is nominally equal to the period during which ten individual bits of data (comprising one byte or two symbols) are serially transferred between two nodes. The time required for serial transfer of each individual bit of data is referred to as a "bit time." Therefore, in a pre¬ ferred embodiment of the invention, the transmit and local multibit clock signals have periods equal to ten bit times, and the symbol clock signal has a period equal to five bit times.

In a preferred embodiment of the invention, data is written into elasticity buffer 12 using the transmit byte clock signal provided by clock generator circuitry 14, and data is read from elasticity buffer 12 using the local byte clock signal provided by clock generator circuitry 14. As embodied herein, the transmit byte clock signal is used to drive a framer 16, a write (input) controller 18, a write (input) pointer 20, a temporary address memory 22, and a num¬ ber of multibit storage elements 24. The local byte clock signal is used to drive a read (output) controller 26, a read (output) pointer 28, a read (output) buffer 30, and a syn¬ chronizer 32.

In accordance with the invention, the elasticity buffer includes receiving means for providing in parallel format, in response to a transmit multibit clock signal that is in sychronism with an independent clock of the upstream

- -5-

node, a multibit data unit having a fixed number of bits of data received from the upstream node. In a preferred embodi¬ ment, this means is provided by ten buffer input data lines 34 (Figures 1 and 2) and may also include framer 16.

Input data is clocked into framer 16 from the clock and data conversion chip one symbol (five bits) at a time using both the rising (TBYTECLK H) and falling (TBYTECLK L) edges of the transmit byte clock signal from clock generator circuitry 14. Framer 16 accepts five-bit wide parallel data from the clock and data conversion chip (not shown). The clock and data conversion chip in repeater node 10 receives input data from the upstream node and provides TTL-compatible data to framer 16 synchronously with the rising edge of the transmit byte clock signal. With each rising edge of the transmit byte clock signal, one byte of data is clocked out of framer 16 onto ten buffer input data lines 34 for input to one multibit storage element 24.

Figure 2 shows the structure for framer 16 in re¬ peater node 10, which is coupled to an FDDI network. Gener¬ ally, incoming data to elasticity buffer 12 is not framed into proper FDDI symbols. For this reason, framer 16 is at the input stage of elasticity buffer 12 to align input data to form proper symbols before input data is tranferred through the elasticity buffer.

The elasticity buffer of the present invention may include means for detecting receipt by the repeater node of a first multibit data unit of a frame from the upstream node. Preferably, this detecting means is provided by compare logic 36 in framer 16. In the FDDI protocol, the first byte in a new frame contains a starting delimiter consisting of the symbols J and K. Compare logic 36 detects the presence of the starting delimiter at the beginning of each frame. Framer 16 uses the starting delimiter to determine proper symbol boundaries for input data received from the upstream node.

In addition to compare logic 36, framer 16 includes a symbol (five bit wide holding register 38, a 29-bit wide

three-part shift register 40, and a multiplexer 42. When a first symbol of input data from the clock and data conversion chip is clocked into framer 16, the first symbol is stored in symbol-wide holding register 38 on the falling edge (TBYTECLK L) of the transmit byte clock signal. On the rising edge (TBYTECLK H) of the transmit byte clock signal, a second sym¬ bol from the clock and data conversion chip, together with the first symbol stored in holding register 38, are shifted into a first part 40A of shift register 40, which is one byte (ten bits) wide. At the same time, data previously stored in shift register part 40A is shifted into a shift register part 40B, which is also one byte wide, and the nine least signifi¬ cant bits of data previously stored in shift register part 40B are shifted into a shift register part 40C, which is nine bits wide. Any data previously stored in shift register part 40C, as well as the most significant bit previously stored in shift register part 40B, is discarded on the rising edge of the transmit byte clock signal.

In the FDDI protocol, the starting delimiter field at the start of each frame consists of the JK symbol pair, which corresponds to the code group 1100010001. Compare logic 36 is coupled to shift register parts 40A and 40B and checks for the pre ence of this ten-bit starting delimiter code group. The starting delimiter code group first appears in one of ten possible paths (i.e., shift register bits 0-9, 1-10, 2-11, ..., or 9-18). When compare logic 36 detects the presence of the starting delimiter code group in one of these ten paths, a JK detect signal is provided by compare logic 36 to write (input) controller 18 on two lines.

In framer 16, after detection of a starting delimiter, the appropriate path within the framer is selected so that the input data received from the upstream node can correctly be provided as buffer input data to one storage element 24. On the next rising edge of the transmit byte clock signal, an output path is selected that corresponds to the particular bits in shift register 40 in which the starting delimiter was detected. Multiplexer 42 establishes

the appropriate output path by selecting a group of ten con¬ secutive bits in shift register parts 40B and 40C for output on ten buffer input data lines 34. Once an output path is selected by multiplexer 42, it remains selected until a starting delimiter is detected in one of the other nine groups of shift register bits.

In accordance with the invention, elasticity buffer 12 has storage means including a fixed number of multibit storage elements, coupled to the receiving means, for storing the multibit data unit in parallel format in one of the stor¬ age elements, wherein each storage element has a unique address. As embodied herein, the storage means is provided by at least four and preferably eight multibit storage ele¬ ments 24, each of which stores one byte (ten bits) of data.

As shown in Figures 3A and 3B, in a preferred embodiment of the storage means one byte of buffer output data is provided on ten buffer output data lines 44A-44J for subsequent transmission to a downstream node. The storage means receives as inputs the transmit byte clock signal, one byte of buffer input data received from the upstream node on buffer input data lines 34, a write address on eight (decoded) write address selection lines 46, and a read address on three (encoded) read address selection lines 48.

A preferred structure for one of the eight storage elements 24 is shown in Figure 3A. Storage element 24 in¬ cludes ten flip-flops 50A-50J, each flip-flop storing one of the ten bits in a byte of data. When the unique address cor¬ responding to this storage element is selected as a write address, a signal is provided on decoded write address selec¬ tion line 46 coupled to that storage element, and no signals are provided on the other seven decoded write address selec¬ tion lines. The providing of a signal on this write address selection line causes enable logic 52 to couple each buffer input data line 34 to a corresponding flip-flop 50. As a result, a byte of input data is written into storage element 24 when the flip-flops are clocked by the transmit byte clock signal.

Preferably, ten multiplexers 54 are provided, as shown in Figure 3B, to select one of eight storage elements 24 for coupling to buffer output data lines 44. One multi¬ plexer 54 is coupled to each buffer output data line 44 and corresponds to a single bit in the multibit data unit. Each multiplexer 54 receives one bit from each one of the eight storage elements 24. In a preferred embodiment, three encoded read address selection lines 48 are used to des gnate the read address and are also input to multiplexers 54. The read address corresponds to the unique address of one se¬ lected storage element 24, and multiplexers 54 respond by coupling flip-flops 50 of the selected storage element 24 to buffer output data lines 44.

In accordance with the invention, parallel asynchronous elasticity buffer 12 includes transmitting means, coupled to the sto age means, for providing in paral¬ lel format, in response to a local multibit clock signal that is in synchronism with the independent clock of the repeater node, one of the multibit data units stored in the storage means. Preferably, the transmitting means is provided by ten buffer output data lines 44 shown in Figure 1, and may also include read (output) controller 26 and read (output) buffer 30.

In a preferred embodiment, repeater node 10 may in¬ clude read (output) buffer 30. As shown in Figure 1, buffer 30 receives ten bits of output data over lines 55 from read controller 26. Read controller 26 receives one byte of data from the storage means on ten buffer output data lines 44. The read controller is provided between the storage means and buffer 30 to add additional idle bytes to the preamble under certain circumstances in order to expand the gap between two frames. Output logic (not shown) in controller 26 either provides the buffer output data from the storage means to buffer 30, or else responds to a force signal by providing an idle line-state byte to buffer 30.

On each falling edge of the local byte clock sig¬ nal, the output data from read controller 26 is loaded into

EET

an input stage of buffer 30. On the rising edge of the byte clock signal (BYTCLK H) , output data in the input stage of buffer 30 is then clocked into an output stage of buffer 30. In this way, output data is retimed from the local byte clock signal provided by clock generator circuitry 14 to the byte clock signal provided by the local ocillator in node 10. On the rising edge of the byte clock signal, the five most sig¬ nificant bits in one byte (i.e., the high order symbol) are provided from the output stage of buffer 30 on five output lines 56 for one symbol time. On the falling edge of the byte clock signal, the five least significant bits in the byte (i.e., the low order symbol) are provided from the out¬ put stage of buffer 30 on output lines 56 for one symbol time.

In accordance with the invention, there is provided write pointer means, coupled to the storage means, for se¬ lecting as a write address the address of a storage element to store the next multibit data unit provided by the receiving means. As embodied herein, the write pointer means may correspond to write (input) pointer 20.

In a preferred embodiment, write (input) pointer 20 is a counter clocked by the transmit byte clock signal. Write pointer 20 generates a write address corresponding to the address of one selected storage element 24 by incre¬ menting the input pointer count in response to the transmit byte clock signal. Pointer 20 provides the write address to each of eight storage elements 24 on eight decoded write address selection lines 46, and also provides the write address to temporary memory 22 and synchronizer 32 on three encoded write address selection lines 58A-58C.

A preferred structure for write pointer 20 is shown in Figure 4. Write pointer 20 is a free running 3-bit counter having eight possible states. Each state corresponds to a unique address designating a single storage element 24 to store the buffer input data on lines 34. Flip-flops 60A-60C provide a three-bit input pointer count (IP) as the write address on three encoded write address selection lines

58A-58C. The outputs from flip-flops 60 are also supplied as inputs to decoder logic 62, which decodes the three-bit write address and provides a signal on only one of the eight decoded write address selection lines 46A-46H.

As embodied herein and as shown in Figure 4, write pointer 20 is a gray code counter. Counter logic 64 gener¬ ates the next write address for input to flip-flops 60 by using the input pointer count (IP) currently output by flip-flops 60. Counter logic 64 changes the state of one and only one bit of the input pointer count (IP). The count pro¬ ceeds in a sequence such as the following: 000, 001, 011, 010, 110, 111, 101, 100, and then returns to 000.

The invention includes read pointer means, coupled to the storage means, for selecting as a read address the address of a storage element to provide the next multibit data unit output by the transmitting means, wherein each multibit data unit is output in first-in, first-out order. Preferably, the read pointer means is provided by read (out¬ put) pointer 28.

In a preferred embodiment shown in Figure 5, read (output) pointer 28 is a loadable counter clocked by local byte clock signal LBYTECLK. Read pointer 28 increments the output pointer count (OP) in response to local byte clock signal LBYTECLK, and selects a single one of eight storage elements 24 to provide the next byte of buffer output data on buffer output data lines 44. Flip-flops 66A-66C provide a three-bit output pointer count (OP) as the read address on three encoded read address selection lines 48A-48C to multi¬ plexers 54, which select the bits stored in one of the eight storage elements for output. The read address on encoded read address selection lines 48 is also provided to synchro¬ nizer 32.

As embodied herein, read pointer 28 is a gray code counter. Counter logic 68 generates the next read address for input to three flip-flops 66 using the output pointer count (OP) currently output by flip-flops 66. Counter logic 68 changes the state of one and only one bit of the output pointer count (CP).

S EET

In the present invention, initialization means is provided for initializing the elasticity buffer to prevent simultaneous selection of the same address as a read address and a write address, wherein in response to initialization, a write address is selected as a read address after a predeter¬ mined delay. In a preferred embodiment, the initialization means may include synchronizer 32, write (input) controller 18, and read (output) controller 26.

A preferred embodiment of write (input) controller 18 is shown in Figure 6. Controller 18 receives the JK detect signal provided by compare logic 36 in framer 16, the buffer input data provided on ten buffer input data lines 34 by multiplexer 42 in framer 16, and the transmit byte clock signal TBYTECLK provided by clock generator circuitry 14. A function of write (input) controller 18 is to detect the presence of two conditions which result in resetting of elas¬ ticity buffer 12. Controller 18 generates an enable signal which is provided to synchronizer 32 on line 71 and a pre-enable signal which is provided to temporary address mem¬ ory 22 on line 69.

As shown in Figure 6, write controller 18 includes input error overlook circuitry 70. Error overlook circuitry 70 is a state machine that functions as an error filter. Circuitry 70 monitors the data on ten buffer input data lines 34 and is responsive to the transmit byte clock signal TBYTECLK. In a preferred embodiment for use in FDDI net¬ works, repeater node 10 receives from the upstream node a preamble including a number of idle line-state bytes, which occurs prior to transmission of thi starting delimiter for the next frame of data. After one idle line-state byte is detected, circuitry 70 provides an input idle counter enable signal IICE. Circuitry 70 continues to provide the input idle counter enable signal until at least two consecutive bytes are detected that do not correspond to idle line-state bytes. Circuitry 70 thereby prevents a single byte error during transmission or detection of a string of idle line-state bytes from interfering with reset of the buffer.

Preferably, controller 18 includes an input idle counter 72. Counter 72 is enabled by the input idle counter enable signal IICE, and is reset when the enable signal from circuitry 70 is not provided. Counter 72 is a four-bit counter clocked by the transmit byte clock signal TBYTECLK that keeps track of the number of idle line-state bytes re¬ ceived by repeater node 10 from the upstream node. Counter 72 provides an input idle count flag sixteen signal IICF16 whenever sixteen consecutive idle line-state bytes have been provided on buffer input data lines 34 by framer 16. Sixteen idle line-state bytes have passed through framer 16 when counter 72 reaches a count of fifteen.

In a preferred embodiment of repeater node 10, elasticity buffer 12 is initialized (reset) vhenever con¬ troller 18 detects one of two possible reset conditions: (1) receipt of sixteen consecutive idle line-state bytes from the upstream node; or (2) receipt of the first byte of data in a frame from the upstream node. As shown in Figure 6, the JK detect signal (on two lines) from framer 16 and the IICF16 signal are provided to three AND gates 74. AND gates 74 in combination with an OR gate 76 indicate that controller 18 has detected the presence of a reset condition.

As shown in Figure 6, an input wait timer 78 is preferably included in write controller 18. Input wait timer 78 is a 12-state counter which increments when clocked by the transmit byte clock signal TBYTECLK until it returns to its initial state. A timer signal is provided by timer 78 when¬ ever it is in this initial state. Input wait timer 78 leaves the initial state when write controller 18 provides a pre-enable signal on line 69 in response to detection of either of the two reset conditions. Therefore, after the pre-enable signal and the enable signal are provided by write controller 18 in response to detection of a reset condition, timer 78 provides a waiting period of twelve byte times before it returns to the initial state. The timer signal is not provided during this waiting period to ensure that ade¬ quate time exists for completion of a previous initialization

-2?-

of elasticity buffer 12. The timer signal is provided to AND gates 74, which permits controller 18 to provide the pre-enable and enable signals if a reset condition is detected, unless initialization of buffer 12 commenced within the waiting period provided by timer 78.

In a preferred embodiment of write controller 18, three flip-flcps 80A-80C are provided that are coupled to an OR gate 82, which provides the enable signal. These flip-flops are responsive to either the rising (TBYTECLK H) or falling (TBYTECLK L) edge of the transmit byte clock sig¬ nal. This circuitry ensures that write controller 18 pro¬ vides the enable signal for two full cycles of the transmit byte clock signal TBYTECLK. On the falling edge of transmit clock byte signal TBYTECLK immediately following the detec¬ tion of a reset condition, the enable signal will be provided if input wait timer 78 is in its initial state. The enable signal is provided for two byte times, i.e., until the fall¬ ing edge of the third transmit byte clock signal following detection of a reset conditions.

In a preferred embodiment of the invention, elas¬ ticity buffer 12 includes memory means for storing at least one initialization address. The memory means, in response to detection of the first multibit data unit of a frame, stores from the write pointer means as the initialization address for the read pointer means the write address corresponding to the storage element selected to store the first multibit data unit.

As shown in Figure 1, the memory means may be pro¬ vided by temporary address memory 22. Temporary address mem¬ ory 22 receives as inputs the pre-enable signal on line 69 from write controller 18, the input pointer count (IP) on lines 58 from write pointer 20, and the transmit byte clock signal TBYTECLK. Temporary address memory 22 preferably con¬ tains flip-flops for storing as the initialization address for read pointer 28 the input pointer count corresponding to the storage element which is selected to store the first byte (i.e., the starting delimiter) in a frame. The

-24-

initialization address is provided on three lines by tempo¬ rary address memory 22 to read pointer 28 and is designated as the address-in-memory (AIM) signal. On the rising edge of the transmit byte clock signal following providing of the pre-enable signal by write controller 18, the input pointer count is incremented by write pointer 20, and this write address is loaded into temporary address memory 22.

The preferred asynchronous elasticity buffer is synchronized only once during transmission of each frame of data. In synchronous elasticity buffers, each data unit written into the buffer is pre-synchronized, increasing the probability of errors due to metastability. In contrast, in the preferred embodiment of the invention, the read and write operations are asynchronous (write operations are in synchro¬ nism with the transmit clock byte signal and read operations are in synchronism with the local clock byte signal).

In a preferred embodiment of the invention, syn¬ chronizer 32 is provided to synchronize the writing and reading of the storage means once per frame of data. Prefer¬ ably, synchronization, as well as initialization, occurs in response to receipt of the first byte in a new frame. How¬ ever, other embodiments of an asynchronous elasticity buffer can be constructed with equivalent circuitry in which syn¬ chronization and/or initialization of the elasticity buffer occurs at another time among various times before, after, or during transmission of each frame.

A preferred embodiment of synchronizer 32 is shown in Figure 7. Synchronizer 32 receives the enable signal on line 71 from write controller 18 and provides an output con¬ troller enable flag signal OCEF to read controller 26 on line 83. The enable signal is provided by write controller 18 for two full cycles of transmit byte clock signal TBYTECLK, and is provided beginning on the falling edge of transmit byte clock signal TBYTECLK following detection of a reset condi¬ tion. In synchronizer 32, the enable signal is sampled by a dual rank synchronizer including three flip-flops 84A-84C on the falling edge of the local byte clock signal. The output

0 ,_ _.

-25-

controller enable flag signal OCEF is provided if the enable signal is present when sampled by the falling edge of local byte clock signal LBYTECLK, except synchronizer 32 does not provide output controller enable flag signal OCEF to read controller 26 for more than two local byte clock signal peri¬ ods.

As shown in the Figure 1 embodiment, the elasticity buffer includes read (output) controller 26. Read controller 26 receives as inputs one byte of buffer output data on lines 44, local byte clock signal LBYTECLK, output controll * enable flag signal OCEF from synchronizer 32, and an equal signal from read pointer 28. In response to these inputs, read controller 26 provides one byte of output data to read (output) buffer 30 on lines 55, and provides a read pointer load enable signal LOAD to read pointer 28 on line 85.

As embodied herein and shown in Figure 8, read con¬ troller 26 includes idle detection circuitry 86. Circuitry 86 receives a byte of buffer output data from one storage element 24 via lines 44. For an FDDI network, the 5-bit code group corresponding to an idle symbol corresponds to 11111. Therefore, an idle byte is detected by inputting the buffer output data to AND gates 88A-88B. In a preferred embodiment, read controller 26 can force an idle byte to be substituted for the actual buffer output data on lines 44 by providing a force signal. The force signal is also monitored by idle detection circuitry 86. The force signal is input to an OR gate 90 along with the output from an AND gate 88C. OR gate 90 provides an idle byte detection signal on line 91 whenever an idle byte is being transmitted from read controller 26 to read buffer 30 and the downstream node.

Preferably, read controller 26 includes an output idle counter 92, as shown in Figure 9. Output idle counter 92 is an eight state counter which keeps track of the number of successive idle bytes provided to read buffer 30. Whenev¬ er idle detection circuitry 86 detects idle bytes on buffer output data lines 44 or the presence of the force signal, the idle byte detection signal on line 91 is input to AND gates

_ _{2 g} _

94A-94C. As long as idle bytes are being transmitted to the downstream node, AND gates 94A-94C provide outputs to three flip-flops 96A-96C that enable incrementing of counter 92 on the following falling edge of local byte clock signal LBYTECLK. When counter 92 reaches the final state, it re¬ mains in that state, indicating that at least eight idle bytes have been transmitted to the downstream node. Output idle counter 92 is reset only when idle detection circuitry 86 indicates that idle bytes are no longer being transmitted to the downstream node. Each flip-flop 96 provides one bit in the three-bit output idle count, which is referred to as output idle count signal OIC.

In the preferred embodiment, the output idle count signal is utilized by read controller 26 in determining the number of idle bytes that are being transmitted to the down¬ stream node. As shown in Figure 9, an output idle count flag eight signal 0ICF8 is provided by logic 98 in read controller 26 whenever the output idle count signal indicates that eight or more idle bytes are being transmitted to the downstream node. Similarly, logic 100 in read controller 26 asserts an output idle count flag seven signal OICF7 whenever counter 92 indicates seven or more idle bytes are being transmitted to the downstream node.

As embodied herein, the read controller performs a process that requires the storage means in elasticity buffer 12 to be progressively more full when initialization occurs before deleting idle bytes from the preamble preceding a sub¬ sequent frame. For a repeater node connected to an FDDI net¬ work, the minimum number of idle bytes between frames is six and the initial number of idle bytes provided between frames by a source node is eight.

In order to implement the preferred process, elas¬ ticity buffer 12 includes additional storage elements 24 so that read controller 26 can wait an additional time period before having to add or delete one or more idle bytes from the preamble. 3 embodied herein, implementation of the process requires the use of a total of eight storage elements

24, wherein four of these elements are additional storage elements provided to increase the range of buffer 12 by forty bits (four bytes) .

In selecting a process for avoiding unnecessary shrinkage of the interframe gap, a trade-off is made between lowering the probability of deletion of idle bytes resulting in the preamble having fewer than a minimum number of idle bytes, and increasing the number of storage elements 24 and the amount of delay in transmission. In the preferred embodiment, a method and apparatus is provided that uses mul¬ tiple thresholds in order to achieve the best results when these factors are considered.

Table I illustrates the use of multiple thresholds in an elasticity buffer. However, the buffer delays in Table I are for a buffer that does not include any circuitry for error detection. When additional hardware included in a pre¬ ferred embodiment of the invention to detect impending error conditions is considered, the buffer delay increases by ten additional bits for reasons that will be explained later.

TABLE I

Number of Elasticity Buffer

Idle Bytes Delay in Bits greater than 8 5-15

8 5-25

7 15-45

6 35-55 less than 6 45-55

The decision of whether to add or delete an idle byte from the preamble is a function of the number of idle bytes being transmitted to the downstream node as well as the fullness of the elasticity buffer. The fewer the number of idle bytes being transmitted, the closer to overflow elasticity buffer 12 must be before another idle byte will be deleted. Using this process, elasticity buffer 12 is four bytes larger than would otherwise be necessary, the maximum node delay is in¬ creased by 320 nanoseconds (four bytes), and the average node delay is increased by forty nanoseconds (five bits). If the

process illustrated above is not utilized, the elasticity buffer delay will be at least 5-15 bits regardless of the number of idle bytes in the preamble being transmitted. In contrast, the illustrated process increases the size of the initial delay as the gap between frames becomes smaller.

Preferably, read controller 26 includes a reset state machine 102, which is shown in Figure 10. Addition¬ ally, the process implemented by reset state machine 102 is illustrated by a state diagram in Figure 11.

In accordance with the invention, the write pointer means and/or the read pointer means may select an ini¬ tialization address stored in the memory means in response to a control signal from the initialization means. Preferably, reset state machine 102 is a six-state sequential machine which utilizes the number of idle bytes counted by output idle counter 92 to determine when to provide a read pointer load enable (load) signal on line 85, which corresponds to the control signal. The read pointer load enable signal pro¬ vided by reset state machine 102 to read pointer 28 causes the read pointer to be loaded with the stored initialization address (AIM) provided by temporary address memory 22, as shown in Figure 5. Initialization (resetting) of read point¬ er 28 causes selection of the storage element containing the starting delimiter for the subsequent frame. In response to initialization, the write address selected by write pointer 20 is selected as a read address by read pointer 28 after a predetermined delay. Providing of the load signal by reset state machine 102 thereby enables transmission of the starting delimiter to the downstream node.

As shown in Figure 10, reset state machine 102 in¬ cludes three flip-flops 104A-104C that provide the three-bit reset state signal RS that indicates the current state. The reset state signal RS is provided to an AND gate 106 which asserts the read pointer load enable signal when reset state machine 102 is in state 100. The inputs to flip-flops 104 are provided by logic 108, which is responsive to the output controller enable flag signal provided from synchronizer 32

on line 83, and to output idle count and output idle count flag signals provided by output idle counter 92.

As shown in Figure 11, reset state machine 102 usu¬ ally loops in idle state 000 until the output controller enable flag signal OCEF is provided. In response to the pro¬ viding of OCEF, the output idle count signal OIC is sampled on the next rising edge of the local byte clock signal.

When the OCEF signal is provided and the output idle count flag eight signal OICF8 has been set, state ma¬ chine 102 proceeds to state 100. The OICF8 signal indicates that eight or more idle bytes are being transmitted to a downstream node. (Although only seven or more idle bytes have actually been detected at this time, an additional idle byte will be transmitted before reset state machine 102 can return to idle state 000.) During the reset state 100, the load signal is output to read pointer 28 on line 85. Read pointer 28 is driven by the falling edge of local byte clock signal LBYTECLK and will therefore select the address of the storage element containing the starting delimiter for the subsequent frame on the falling edge of the local byte clock signal following entry of reset state machine 102 into reset state 100. The count of eight idle bytes is more than a high threshold number of idle bytes, which is preferably set to equal seven bytes. Therefore, as shown in Table I, the delay immediately after initialization in selecting the write address as the read address is always at least five bit times, but transmission of the starting delimiter for the subsequent frame may be further delayed by read controller 26.

When eight or more idle bytes are not being trans¬ mitted to the downstream node, reset state machine 102 pro¬ ceeds from state 000 to state 001 in response to the OCEF signal indicating receipt of the starting delimiter for the subsequent frame. Reset state machine 102 remains in state 001 for one byte time and monitors whether the output idle count flag seven signal OICF7 is provided indicating that seven idle bytes are being transmitted to the downstream node.

If seven idle bytes are being transmitted to the downstream node, state machine 102 proceeds from state 001 to reset state 100, and then performs in the manner previously described. When the high threshold number of seven idle bytes is being transmitted to the downstream node, the load signal is not provided by read controller 26, thereby delay¬ ing transmission of the starting delimiter to the downstream node even though the write address has been selected as the read address. Since reset state machine 102 has to proceed to state 001 before it enters the reset state 100, transmis¬ sion of the starting delimiter is delayed for one additional byte time compared with a situation in which eight or more idle bytes are being transmitted. Thus, as shown in Table I, the minimum elasticity buffer delay is 15 bit times when seven idle bytes are being transmitted.

If fewer than seven idle bytes are counted by out¬ put idle counter 92, reset state machine 102 proceeds from state 001 to state 011, where it remains for one byte time. If fewer than seven idle bytes are counted by output idle counter 92, reset state machine 102 then proceeds to state 111, where it remains for an additional byte time. When the output idle count signal indicates that six idle bytes, which preferably corresponds to a low threshold number, are being transmitted to the downstream node, then reset state machine 102 can proceed from state 111 to reset state 100. Thus, in response to an idle byte count indicating that a low thresh¬ old number of six idle bytes is being transmitted to the downstream node, reset state machine 102 does not provide the load signal, thereby delaying transmission of the starting delimiter to the downstream node for an even longer time pe¬ riod. Reset state machine 102 is required to enter two addi¬ tional states before it enters reset state 100 and arserts the control signal. This corresponds to the process shown in Table I, in which an idle byte count of six results in a min¬ imum delay that is two byte times longer than the minimum delay when seven idle bytes are being transmitted to the downstream node.

At times when output idle counter 92 indicates that fewer than six idle bytes are being transmitted to the down¬ stream node, state machine 102 proceeds from state 111 to state 110, where it remains for one byte time. As long as two or more idle bytes are being transmitted to the down¬ stream node, or if the read address (OP) equals the stored initialization address (AIM), reset state machine 102 will then proceed to reset state 100. In this situation, reset state machine 102 enters four additional states before pro¬ ceeding from idle state 000 to reset state 100. Thus, when a lower threshold number of idle bytes equal to five or less is being transmitted to the downstream node, transmission of the starting delimiter is delayed for an additional byte time. As shown in Table I, the minimum elasticity buffer delay is 45 bits whenever fewer than six idle bytes are being trans¬ mitted to the downstream node.

In unusual situations, reset state machine 102 may leave state 110 and proceed to initial state 000 without detection of a single idle byte. This may occur if the write and read pointers have drifted far from their initial spacing. In this situation, data may be deleted by repeater node 10 if reset state machine 102 enters the reset state 100. Therefore, if one idle byte has not been detected, and if the read address (OP) does not equal the stored ini¬ tialization address, state machine 102 proceeds directly from state 110 to the initial state 000, and no initialization (reset) of elasticity buffer 12 occurs.

As embodied herein, read pointer 28 provides an equal signal to read controller 26 to indicate that elastic¬ ity buffer 12 is ready to begin transmitting the first byte of the subsequent frame to the downstream node. The equal signal is provided by read pointer 28 when the output pointer count (OP) matches the stored initialization address (AIM). This occurs only when the storage element 24 selected by read pointer 28 to provide buffer output data to buffer 30 (via read controller 26) contains the first byte (the starting delimiter) in the subseσuent frame.

Preferably, read controller 26 includes a force idle state machine 110, as shown in Figure 1. State machine 110 functions to cause additional idle bytes to be trans¬ mitted to the downstream node whenever the load signal is not being provided, even though the equal signal provided by read pointer 28 indicates that buffer 12 is otherwise ready to begin transmitting the first byte (the starting delimiter) of the subsequent frame. Force idle state machine 110 works in conjunction with reset state machine 102 in order to add idle bytes to the preamble between frames whenever transmission of the first byte in a subsequent frame is delayed because the output idle count signal from output idle counter 92 indi¬ cates the number of idle bytes being transmitted to a down¬ stream node is at or below a certain threshold.

In the preferred embodiment of the invention, the elasticity buffer is initialized by providing a loadable read pointer 28 and free-running write pointer 20, and loading a write address selected by write pointer 20 into read pointer 28 as a read address after a predetermined delay. However, an elasticity buffer in accordance with the present invention can be provided using other equivalent circuits. For exam¬ ple, the write pointer means may correspond to a loadable counter, while the read pointer means corresponds to a free-running counter. In such an embodiment, initialization can be performed by loading the write pointer means with an initial write address that will be selected by the free-running read pointer means after a predetermined delay. In another embodiment, both the read pointer means and the write pointer means may be loadable. In this embodiment, initialization may be performed by loading different addresses into the read pointer means and the write pointer means. The initial read address . ^' or the read pointer means is selected so that a predetermined delay will occur before the read pointer means selects as the read address the ini¬ tial write address which was loaded into the write pointer means. Other possible embodiments of the invention may in¬ clude one or more state machines for selecting the read

and/or write addresses such that a predetermined delay elapses before a particular write address is selected as a read address.

In accordance with the invention, the elasticity buffer includes detection means for detecting whether an error condition corresponding to a write overflow or read underrun of a storage element is impending by determing whether the same address is selected as the write address and the read address during an overlap time period having a dura¬ tion equal to a threshold time period. As embodied herein and shown in Figure 12, the detection means may be provided by overflow/underrun detection circuitry 112.

Immediate and reliable detection of an overflow and/or under-run condition is extremely difficult to perform if data is asynchronously entering and leaving an elasticity buffer. However, by monitoring the read and write addresses for the elasticity buffer, it is possible to detect when an overflow/under-run condition is impending. For example, if each storage element in the elasticity buffer contains ten bits (one byte in the FDDI protocol), then the elasticity buffer is on the verge of overflow or underrun of a storage element when both the read pointer and write pointer select the same address for ten bit times (relative to either the local or transmit byte clock signal).

An overflow or underrun of a storage element occurs when that storage element is being written to and read from at the same time. Furthermore, because of the finite propa¬ gation delays and set-up and hold times associated with the logic in an elasticity buffer, it is impossible for data to remain uncorrupted if a single storage element is being writ¬ ten to and read from at precisely the same time. Therefore, data corrup ion occurs before actual overflow or underrun of a storage element if data is read from that storage element too soon after being written. Thus, it is important for a detection means to indicate that an overflow or an underrun condition is impending before an overflow/underrun occurs, thereby preventi:.g corrupted data from being transmitted through the elasticity buffer without being flagged.

As an example, the time when the detection means must detect that a write overflow or read underrun of a stor age element is impending can be calculated. It is assumed that a parallel asynchronous elasticity buffer is provided in which each storage element contains ten bits (one byte) of data, and in which valid data is obtained only if data is read from a storage element at least four bit times after it is written. In this example, in order to guarantee that no corrupted data will pass through the elasticity buffer with¬ out being flagged, the detection means must detect that a write overflow or read underrun is impending whenever the read pointer and write pointer select the same address for an overlap time period of six bit times or less.

Asynchronous operation of the read and write point¬ ers makes determination of the exact amount of any overlap in the two pointers a non-trivial task. However, it is not as difficult to determine when the two pointers overlap (i.e., select the same address as the write address and the read address) during an overlap time period falling within a given range. Furthermore, if the independent clocks in the up¬ stream node and the repeater node can be assumed not to dif¬ fer in frequency by a large amount (i.e., 50% for the follow¬ ing examples), then only one independent clock need be used in sampling the read and right ointers to determine the amount of pointer overlap. If this assumption is not valid, the same basic detection approach can be used, although the detection means becomes more complicated because both the transmit byte clock signal and the local byte clock signal must be sampled in order to determine the amount of pointer overlap.

The use of asynchronous read and write pointers in the elasticity buffer makes it necessary to utilize gray code counters for the pointers. Pointer overlap is detected by sampling of the output and input pointer counts. However, if one of the two pointers increments its count immediately before sampling, an uncertainty exists concerning the state of any bits tha were changed. For example, if a count

SHEET

changes from 111 to 000, there is a possibility of glitching of the output because it is possible to interpret the count as having any of eight possible values. However, gray code counters provide counts that change only one bit at a time and which can only be interpreted as one of two consecutive counts, thereby preventing gliching of the output and reduc¬ ing the probability of false error detection.

In a preferred embodiment of the invention, the elasticity buffer includes means for providing one or more sampling clock signals. In this preferred embodiment, the detection means also includes comparator means for comparing, in response to the sampling clock signal, the write address and the read address. Preferably, the sampling clock signal or signals are in synchronism (i.e., maintain a fixed phase relationship) with the local byte clock signal, as opposed to the transmit byte clock signal. As embodied herein, and as shown in Figure 12, overflow/underrun detection circuitry 112 uses a first sampling clock signal provided by the sampling clock signal providing means to detect whether a write over¬ flow is impending, and uses a second sampling clock signal out of phase with the first sampling clock signal to detect whether a read underrun is impending. Preferably, the first sampling clock signal is approximately 270° out of phase with the local byte clock signal, and the second sampling clock signal is approximately 180° out of phase with the local byte clock signal.

A preferred embodiment of a sampling clock signal providing means for providing a first sampling clock signal to detect whether a write overflow is impending and a second sampling clock signal out of phase with the first sampling clock signal to detect whether a read underrun is impending is shown in Figure 13. In this embodiment, clock generator circuitry 14 receives as inputs from a local oscillator the byte clock signal and a symbol clock signal.

Clock generator circuitry 14 generates a local byte clock signal LBYTECLK L, wnich will be referred to as the phase zero local byte clock signal, and also generates a

phase 180 local byte clock signal LBYTECLK H and a phase 270 local byte clock signal LBCLK270 H. Each of these outputs represents a different phase of the independent clock in the repeater node. The symbol clock signal from the local oscil¬ lator is required because a signal running at twice the fre¬ quency of the byte clock is needed to easily obtain four dif¬ ferent phases of the local byte clock signal. If only two phases of the local byte clock signal were required, i.e., the phase zero byte clock signal and phase 180 local byte clock signal, then the necessary sampling clock signals can be easily provided using only an inverter. As embodied in Figure 13, the clock generator circuitry includes a flip-flop 114 that provides the phase 270 local byte clock signal, and a flip-flop 116 that provides both the phase zero local byte clock signal and the phase 180 local byte clock signal.

A first case of interest occurs when the local byte clock signal is faster than the transmit byte clock signal. In this case, the read address selected by the read pointer means catches up with the write address selected by the write pointer means. If the read and write pointers are compared, and there is an overlap detected using a comparator means that samples with the phase 180 local byte clock signal, there is an overlap time period having a duration equal to five bit times minus the propagation delay through any comparator logic and the set-up times of any flip-flops in the read and write pointers. Depending on the circuit design and device technology used, these propagation delays and set-up times may have a duration of less than a single bit time. Therefore, under these circumstances, a detection means using the phase 180 local byte clock signal can deter¬ mine that the same address is selected as the write address and the read address during an overlap time period having a duration of between four and five bit times. If the propaga¬ tion delays and set-up times are as high as three bit times, then the overlap time period that can be determined has a duration of between two and five bit times.

HEET

A second case of interest occurs when the transmit byte clock signal is faster than the local byte clock signal. In this case, the write address selected by the write pointer means catches up to the read address selected by the read pointer means. If the detection means includes comparator means that samples the write address and the read address using the phase 270 local byte clock signal, the detection means can determine whether the same address is selected dur¬ ing an overlap time period having a duration equal to 2- ^* *-. bit times, plus the propagation delay through any comparator logic and the set-up times of any flip-flops in the read and write pointers that are sampled. The overlap time period that can be determined by the detection means using the phase 270 local byte clock signal is between 2^ and 3h bit times if the propagation delays and the set-up times have a duration of less than one bit time. If the propagation delays and set-up times have a duration as high as three bit times, then the detection means is able to determine whether the same address is selected as the write address and as the read address during an overlap time period having a duration of between 2h and 5*-≤ bit times. The pointers can also be com¬ pared in this second case using the phase 180 local byte clock signal. If the propagation delays and set-up times have a duration of less than one bit time in these circum¬ stances, then the detection means can determine whether the same address is selected during an overlap time period having a duration of between five and six bit times.

These examples illustrate that when the propagation delays and the set-up times do not have a duration exceeding a single bit time, detection of overflows and underruns can be simplified using only the phase 180 local byte clock sig¬ nal for both conditions to determine whether the same address is selected during an overlap time period having a duration in the range between four and six bit times. If propagation delays and set-up times are assumed to have a duration not exceeding three bit times, the phase 180 local byte clock signal provides a second sampling clock signal for a

comparator means that detects an overlap time period of between two and five bit times for an impending underrun, and the phase 270 local byte clock signal detects an overlap time period having a duration of between 2^ to 5 bit times for an impending overflow.

In the examples described above, apparatus has been described that detects an impending overflow or underrun when the overlap time period has a duration of less than six bit times. For relatively large propagation delays and set-up times, a detection range of between two and 5 bit times is obtained using two different phases of a four-phase clock.

In situations in which the comparison logic is rel¬ atively fast (i.e., propagation delays and set-up times having a duration not exceeding one bit time), the comparator means can detect both impending overflows and underruns using a phase 180 local byte clock signal. The phase 180 local byte clock signal is simp.y the inverted local byte clock signal, thereby eliminating the additional circuitry required to generate a multiphase clock signal.

The detection means of the present invention may be provided using sampling clock signals other than those described herein. Multiphase or higher speed clock signals may be necessary, depending on the speed of the design, the duration of the overlap time period that must be detected by the detection means, and the size of the detection range cor¬ responding to the threshold time period that is acceptable.

The inclusion of detection means in the parallel asynchronous elasticity buffer requires an increase in the amount of storage that must be provided by the storage ele¬ ments. The minimum number of additional bits of storage for purposes of detecting whether a write overflow or read underrun of a storage element is impending is referred to as the overflow/underrun detection overhead. The over- flow/underrun detection overhead is equal to the size of a single storage element (one byte or ten bits) minus the smallest amount of pointer overlap that can be determined by the detection means. When orooaαa ion delays and set-up

UTE SHEET

times have a duration of three bit times or less, and the phase 180 byte clock signal and phase 270 byte clock signal are used to detect an error condition, then the minimum amount of pointer overlap that can be determined equals two bits for underruns and 2h bits for overflows. Therefore, if the local byte clock signal is faster than the transmit byte clock signal, this results in underrun detection overhead of eight bits. Similarly, if the transmit byte clock signal is faster than the local byte clock signal, the overflow detec¬ tion overhead equals l bits.

In accordance with the FDDI protocol, a slippage in clock frequency of at most 4h bit times during transmission of a maximum length frame of data can be expected in a system in which the clocks are operating within prescribed toler¬ ances. The initial spacing in selection of addresses pro¬ vides a predetermined delay of at least fifteen bit times for buffer 12. In order for the read pointer and write pointer to select the same address for ten bit times (i.e., one byte time), the amount of clock slippage during transmission of a frame must equal fifteen bit times. After initialization, the read pointer and write pointer will not select the same address and will not overlap at all until a slippage of at least five bit times has occurred between the transmit byte clock signal and the local byte clock signal. In the pre¬ ferred embodiment of overflow/underrun detection cicuitry 112 shown in Figure 12, an impending write overflow and/or read underrun is detected before actual overflow/underrun occurs when the independent clocks in the upstream node and the re¬ peater node have slipped at least eight bit times with re¬ spect to each other, corresponding to an overlap for more than two bit times.

Overflow/underrun detection circuitry 112 is designed to detect an overlap time period having a duration equal to a threshold time period ranging between two (or 2h ) and five (or 5 ) bit times. In a preferred embodiment, ini¬ tialization causes the read pointer to lag the write pointer by between fifteen and twenty-five bit times, and the amount

of lag can be increased to between fifty-five and sixty-five bit times if idle bytes are added by read controller 26 to the preamble between frames. Therefore, overflow/underrun detection circuitry 112 detects an error condition when clock frequencies or frame length significantly exceed specifica¬ tion but before the actual occurence of a write overflow or read underrun condition, thereby preventing any data corrup¬ tion frc occurring.

As shown in Figure 12, the comparator means may in¬ clude three XOR gates 118 and an OR gate 120. Each of three encoded read address selection lines 48 and three encoded write address selection lines 58 is input to one correspond¬ ing XOR gate 118. If the same address is being selected as the write address and as the read address, the read pointer count (OP) and write pointer count (IP) will be identical. If the read and write addresses are identical, a signal is provided by OR gate 120 to a flip-flop 122, which detects whether a read underrun is impending, and to a flip-flop 124, which detects whether a write overflow is impending. Flip-flop 122 is clocked by the phase 180 local byte clock signal, and flip-flop 124 is clocked by the phase 270 local byte clock signal.

As shown in Figure 12, when the comparator means determines that the same address is selected as the write address and the read address during an overlap time period, a signal is provided to OR gate 126. This signal is provided only if the overlap time period has a duration exceedinc two bit times. The output from OR gate 126 is dual rank synchro¬ nized usir.g the phase 180 local byte clock signal and flip-flops 128A-128C. A VSΞL signal is provided by over- flow/underrun detection circuitry 112 in synchronizer 32 to read buffer 30, where it is retimed to the bye clock signal frcm the local oscillator in the repeater node and output as an elasticity buffer error signal ΞBFERR. The VSΞL signal is also provided by synchronizer 32 to read pointer 28, as shown in Fiσure 5.

SHEE ^"

In read pointer 28 (Figure 5), three multiplexers 130A-130C are provided that are responsive to the load signal and can change the inputs loaded into flip-flops 66. As shown in Figure 5, when the load signal is not provided, mul¬ tiplexers 130A-130C feed back two inverted bits of the output pointer count through counter logic 68 into two corresponding flip-flops 66, and feed back the third bit in the output pointer count unchanged to the remaining flip-flop 66 through counter logic 68. As a result, the output pointer count (OP) is reset to a new read address located four buffer locations away, preventing write overflow or read underrun of a storage element from actually occurring.

In the preferred embodiment of overflow/underrun detection circuitry 112, when read controller 26 provides the load signal at exactly the same time that VSEL is asserted, it is preferable to initialize elasticity buffer 12 in the normal manner, and the VSEL signal is ignored. Ini¬ tialization of the elasticity buffer when the first byte in a new frame is received prevents write overflow or read underrun of a storage element. There is no need to provide an elasticity buffer error signal in this situation because detection circuitry 112 is designed so that detection of an impending overflow or underrun o curs before any data is actually corrupted.

The timing for overflow/underrun detection is il¬ lustrated in Figure 14. Flip-flops 122 and 124 (Figure 12) sample the output of OR gate 120 on each rising edge of the phase 180 local byte clock signal and the phase 270 local byte clock signal, respectively. If a signal is provided by OR gate 126 when it is sampled on either rising clock edge, an error signal is provided by OR gate 126. An impending read underrun condition is detected at clock edge SI and an impending write overflow condition is detected at clock edge S2. If read controller 26 is providing the load signal on clock edge SI, write overflow/read underrun detection is im¬ mediately negated by AND gate 132 shown in Figure 12. If read controller 26 has not yet provided the load signal,

however, an error signal is provided by AND gate 132 to a dual rank synchronizer including flip-flops 128. The error signal is clocked through the dual-rank synchronizer on clock edges S3 and S4. An error signal is provided by flip-flops 128 in the dual-rank synchronizer to flip-flop 134, which delays the error signal for one additional byte time. The output of flip-flop 134, the output of the synchronizer, and a load signal from read controller 26 that has been delayed for one byte time by flip-flop 136 are all input to AND gate 138. The delayed load signal is used to negate an error sig¬ nal indicating detection of an impending overflow and/or underrun. If read controller 26 provides a load signal on clock edge S3, the delayed load signal is provided on S4, the same time that an error signal is provided by flip-flops 128 in the synchronizer. Under these circumstances, AND gate 138 will prevent the VSEL signal from being provided. Thus, if the load svgnal is provided by read controller 26 on clock edge SI or S3, the VSEL signal will not be provided. If read controller 26 does not provide the load signal at either of these times, the VSEL signal will be provided by AND gate 138 to read buffer 30 on clock edge S5.

On clock edge S6, the VSEL signal is no longer pro¬ vided by AND gate 138. An elasticity buffer error signal is provided by read buffer 30 on the rising edge of the byte clock signal provided by the local oscillator, which occurs sometime between S6 and S7. The elasticity buffer error sig¬ nal will stop being provided sometime between S7 and S8.

In the preferred embodiment, the providing of the VSEL signal results in the read pointer being loaded with a read address that is four bytes away from its current posi¬ tion because that address is approximately one half the length of the buffer away. This reset of the read pointer prevents a m.rtastable condition from occurring due to exces¬ sive overlap of the two pointers, but will also cause some data to be reread or lost. However, the providing of an elasticity buvfer error signal by read buffer 30 prevents any data corruption from occurring that is unexpected cr

undetected. In read pointer 28, an OR gate 140 (Figure 5) is provided for monitoring the VSEL signal and the load signal so that a new read address is loaded into flip-flops 66 when either initialization or error detection occurs. On clock edge S5, a new read address is provided by pointer 28, there¬ by eliminating the overlap in selection of the write address and the read address. The read address is moved four bytes away from the previous read address if the VSEL signal is provided by using one bit in the present output pointer count (OP) and inverting the other two bits in the three-bit count. Whenever the elasticity buffer is initialized, data in storage elements 24 may be discarded. However, data cor¬ ruption is prevented by providing interframe gaps consisting of idle line-state bytes between successive frames of data. By initializing the elasticity buffer only during long interframe gaps or at the beginning of a new frame of data, corruption of actual data will not occur since the interframe gaps can be corrupted without concern. The process shown in Table I by which idle line-state bytes may be added to an interframe gap ensures that an adequate interframe gap will exist. This allows any nodes in the network to initialize without corrupting data when the first byte in a new frame is received.

In the preferred embodiment of the elasticity buffer, eight one-byte storage elements are provided. The size of the buffer is calculated by considering several of factors.

Elasticity buffers work on the principle that by writing data into a buffer until it is partially full before any data is read out of the buffer, the buffer is able to accommodate for differences in the speeds at which read and write operations occur. Larger buffers can accommodate for greater speed differences between clocks used for reading and writing. The minimum size of the buffer is determined based on several parameters: (1) the nominal frequency of trans¬ mission of the data units (Fn); (2) the data format (serial or n bits in parallel); (3) the clock tolerance about the

nominal frequency (plus/minus Fd) ; and (4) the maximum number of data units in a frame or packet (L). The maximum allow¬ able clock frequency Fh = Fn + Fd, and the minimum allowable clock frequency Fl = Fn - Fd. Clock slip is defined as the difference in the number of clock cycles between two clocks over some period of time. The maximum amount of clock slip (S) between the clocks used in reading and writing the buffer during transmission of a maxium length frame of data is cal¬ culated (in seconds) to be S = L x (1/F1 - 1/Fh) . If Pb is the nominal period of a bit time in seconds, then the maximum allowable slip in bit times (Sb) is defined as Sb = S/Pb. Therefore, over the course of a maximum length frame, two clocks controlling read and write operations of the buffer may slip relative to each other by as many as Sb bit times.

Therefore, the buffer must have a size at least 2 X Sb bits long in order to accommodate the frequency differ¬ ences that may exist between two clocks within the allowed tolerances. At least Sb bits of buffering in one direction is needed when the the read clock is faster t.an the write clock, and at least Ξb bits of buffering in the other direc¬ tion is needed when the write clock is faster than the read clock.

The size of the buffer is increased to account for the overhead involved in writing to and reading from a buffer. The amount of overhead depends on how over- flow/underrun conditions are detected, on how synchronization between writing and reading of data is accomplished, and on the amount of data that is written into any one storage ele¬ ment at a time. For example, a serial elasticity buffer (in which one bit is written and read at a time) does not have to be as large as a parallel elasticity buffer.

In determining the size of the elasticity buffer for a preferred embodiment of the invention, the maximum allowable clock slip Sb was assumed to equal five bits in view of the FDDI protocol. Furt ^' r rmore, overfiov/underrun detection in the embodiment described herein occurs by determininc whether there is a pointer overlap of at least

two or 2i≤ bits. Additionally, a parallel elasticity buffer is provided, in which each storage element contains one byte, and writing and reading is performed asynchronously in units of one byte.

As discussed previously, the overflow/underrun detection overhead for a preferred embodiment of the inven¬ tion is approximately l bits for overflow detection and approximately eight bits for underrun detection. When the maximum allowable clock slip of five bits is accounted for, an effective pre-buffer contains thirteen bits, and an effec¬ tive post-buffer contains 12-*s bits. Thus, when the elastic¬ ity buffer is initialized (preferably at the beginning of a frame), a write address should not be selected as a read address by a read pointer means for at least thirteen bit times. Similarly, the read pointer means should lead the write pointer means by at least 12^ bit times because the read and write pointers are circular, i.e., a pointer selects the first buffer location after selecting the last buffer lo¬ cation. Thus, the minimum elasticity buffer size equals 25^ bits (12.5 + 13). However, data is written and read one byte at a time in the parallel elasticity buffer. There cannot be any buffer locations containing only partial bytes. As a result, the minimum practical elasticity buffer contains thirty bits, resulting in an effective pre-buffer and post- buffer of fifteen bits each.

An additional factor increasing the size of a prac¬ tical buffer is a result of the asynchronous read and write operations. A specific separation between the read and write pointers cannot be guaranteed because of the asychronous transmit and local byte clock signals. The buffer can only determine whether the separation between the two pointers falls within a specific range. The range of uncertainly in pointer separation is one byte (ten bits). Therefore, the size of an effective buffer must be increased by an addi¬ tional byte (ten bits) due to the uncertainty resulting from synchronization of two asynchronous bvte clock siαnals.

In one practical embodiment of the invention of minimum size, the storage elements in elasticity buffer 12 must provide a total of forty bits (four bytes) of storage. In the preferred embodiment of the invention described here¬ in, however, four additional bytes of storage have been pro¬ vided in order to allow the elasticity buffer to implement an algorithm that will ensure that an interframe gap between consecutive frames of data is maintained.

Timing charts are shown in Figures 15 and 16 that illustrate the timing of the selection of write and read addresses by the write and read pointers. For purposes of this description, the elasticity buffer is assumed to contain only four storage elements, so that the input and output pointer counts contain only two bits. As shown in lines (a)-(g) of Figure 15, at the same time that the starting delimiter for a new frame of data is written into the storage element (line c) designated by write address 10, this write address is stored in the temporary address memory (line f), and an enable signal (line e) is provided to a synchronizer, where it is retimed in accordance with the local byte clock signal. The reclocked enable signal corresponds to the OCEF signal (line b) provided by the synchronizer and shown in Figure 16. After the read controller receives the output controller enable flag signal, a load signal (line c) is pro¬ vided to the read pointer. The load signal received by the read pointer causes the read pointer (line d) to initialize in response to the next local byte clock signal, and the read pointer selects as the read address the initializa ion address 10 stored in the temporary address memory. As a result, the storage element containing the starting delimiter for the new frame of data is selected by the read pointer. One byte time later, the starting delimiter is read out of the storage element (line e). Initialization of the elastic¬ ity buffer occurs in such a manner that the starting delimiter of the new frame is read no sooner than fifteen bit times after it is written into a storage element. Due to the uncertainty in synchronization of up to one byte time, the

starting delimiter will be read out after a delay of between fifteen and twenty-five bit times. Thus, initialization at the start of each new frame guarantees a minimum of fifteen bits of ore-buffering and post-buffering.

It will be apparent to those skilled in the art that various modifications and variations can be made in the elasticity buffer of the present invention without departing from the scope or spirit of the invention. As some examples, the apparatus may be implemented using other circuit compo¬ nents or even software, the node may be included in various types of data communication systems, and the units used may be symbols instead of bytes. Thus, it is intended that the present invention cover any modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.