REFERENCE TO RELATED APPLICATIONS

Some of the subject matter described herein is described and/or claimed in application Serial No. PCT/US86/ 02565, entitled CABLE SYSTEM FOR DIGITAL INFORMATION and filed of even date herewith in the name of William P. Rogers,

BACKGROUND OF THE INVENTION

The present invention relates to methods and apparatus for encoding and transmitting signals and, in a preferred embodiment, to the provision of a cable system suitable for transferring the information in a plurality of parallel signals from one set of conductors to a corresponding remote set of conductors.

There are many situations, particularly in the data communications art, where a plurality of parallel signals on separate conductors are to be conveyed to a more or less remote corresponding set of conductors, in parallel form, for example between a connector plug on "the so-called front-end processor of a computer and a

SUBSTITUTE SHEET

connector plug on a modem through which the signals are to be supplied to a telephone company line, and-, at the other end of the telephone line, between a connector plug on a remote modem and a connector plug on a remote ter- inal equipment. The modems may be located near the ends of the telephone lines in buildings in which one or more computers and/or terminals are housed, while the computers and terminals themselves may be located inside the build¬ ings at various locations relatively remote from the modems.

It is known to accomplish such signal transfer of a plurality of separate parallel signals from one set of conductors to another by a simple multi-conductor cable, one cable conductor for each pair of conductors to be interconnected. When many conductors are involved, such a multi-conductor cable becomes expensive, bulky and awk¬ ward to handle and dress.

It is also known to multiplex parallel signals so that they are, in effect, converted to serial form, and to transmit them over a common transmission channel, which may be a concentric cable, a twisted-pair of wires, an optical fiber cable, or a space-link, as examples. At the receiving end of the cable they are reconverted from serial to parallel form. In its simplest form such a system may comprise a sampling system which periodically samples each parallel input signal to form a time-multi¬ plexed series train of pulses having amplitudes repre¬ senting the original signals, to which appropriate synchro¬ nizing pulses are added once per cycle to identify the start of a sampling cycle, and a resampling system at the receiver which reconstitutes the original separate signals from the transmitted samples. In some cases a

clock signal, timing pulses, or other signals may be trans¬ mitted to permit the receiver to identify accurately the times at which the transmitted samples of particular orig¬ inal parallel signals are received.

Such systems relying upon detection of the ampli¬ tudes of the multiplex pulses to carry the information suffer from the drawback that signal amplitudes depend upon the values of overall system gains, and require ac¬ curate level detection, which can readily lead to errors; in addition, noise and other interfering .signals can easily affect the reliability of the complete system.

In another type of known system, time-multi¬ plexing is again utilized, but instead of relying upon amplitude variations in the pulse samples to represent the information, the pulses are duration modulated, where¬ by the widths (durations) of the pulses indicate the in¬ formation being conveyed. In the case of binary digital information, this has been accomplished by transmitting, within each successive, equal, time interval or time slot in a frame, a pulse having either of two different dura¬ tions depending upon whether a 1 or a 0 is being repre¬ sented.

While such a system is suitable for many pur¬ poses, it does require a substantial effective bandwidth for the transmission channel through which the signal passes and, unless such bandwidth is provided, information will not be reliably transmitted. The larger the required bandwidth the more expensive the input devices, output devices and samplers and, in general, the shorter the transmission line which can be used to transmit informa¬ tion accurately and reliably, since the bandwidth of the

line generally falls off with increasing line length. In general, the higher the sampling rate the greater the bandwidth required.

Assuming a group of parallel input signals (e.g. 16) in binary digital form, it will be understood that in general, in prior-art systems, there will be a maximum permissible time interval between successive samplings of each parallel input signal substantially equal to the shortest time interval for which any of the input signals remains in one of its states, otherwise the sampler may never detect certain states which the input signals assume only briefly during normal operation. If the maximum interval at which each signal must be sampled is P _max then the minimum p ^c ermissible rep ^c etition rate Fmm. of the periodic sampling of each signal is •**-/* ^p _max , and the cor¬ responding minimum bandwidth of transmission channel is BW . , which may readily become undesirably large when

P_max becomes small,

There are also a variety of instances in which in- formation available in parallel form is to be transmitted through a common channel in serial digital form. Such a serial signal may be generated by a parallel-to-serial converter which sequentially and repetitively addresses or samples a set of parallel signals to derive successive pulses having values corresponding to the corresponding contemporaneous values of the several parallel signals. At the other end of the channel, the samples may be passed through a serial-to-parallel demultiplexer which recon¬ stitutes the original parallel signals from the trans- mitted samples. In an especially important form of such systems the parallel signals are binary digital signals having at various times either one of two values or levels, commonly designated as a 0 or a 1.

It is usual in such apparatus to sample all of the parallel signals periodically and at the same rate, sufficiently often that no significant changes occur in any of the parallel signals which are not detected and represented by the samples. In such usual types of system then, each parallel signal is sampled at intervals no greater than the shortest time duration of significant changes in any of the parallel signals. This requirement for sampling all of the signals at a specified minimum rate requires a corresponding minimum bandwidth for the transmission channel, in order to assure accurate and reliable signal transmission over substantial distances. The greater the required bandwidth, the shorter and/or more expensive is the transmission channel which will transmit the signals accurately and reliably.

An object of the present invention is to provide a new and useful information transmission method and system.

A further object is to provide a new information encoding method and system, and a method and system for decoding the encoded information.

Another object is to provide such method and system which are conservative of the amount of bandwidth required for the transmission channel.

It is also an object of this invention to provide a new and useful system and method for transmitting in¬ formation, particularly binary digital information.

Another object is to provide such system and method which are conservative of the channel bandwidth required to transmit the signals accurately and reliably.

A further object is to provide such system and method which, at least for parallel signals having certain characteristics, accomplishes parallel-to-serial conver¬ sion, transmission of the serial signals, and reconsti- tution of the transmitted serial signals into parallel signals, with a required bandwidth smaller than is nec¬ essary in conventional systems.

SUMMARY OF THE INVENTION

These and other objects and features of the invention are achieved by the provision of a method and apparatus for encoding information as to the values of original signals, in which a series of pulses of alternat¬ ing polarities is formed each having a duration representa¬ tive of a corresponding value of the original signals and each beginning substantially immediately after the last-pre¬ ceding pulse. For the encoding of binary digital information- the encoded signal preferably alternates between two fixed levels and remains at each alternate level for either of two different time intervals, depending upon whether the corresponding sample represents a binary 1 or a binary 0 (a High or a Low) . In the preferred embodiment, the original signals are separate parallel signals which are sequentially sampled, the values of the successive samples then being represented by the durations of the corresponding successive pulses produced in accordance with the invention.

Accordingly, the encoded pulses are not period¬ ic and, in the case in which the original signals are sampled, the time required to complete one cycle or "frame" of sampling depends upon the content of the information being conveyed. If, for example, the shorter pulses are used to represent 1's and the longer pulses to represent

O's, then a message containing all l's will have the short¬ est frame time and a message containing all 0's the long¬ est frame time; a mixture of 1's and 0's will have an intermediate frame time.

Significant advantages of this encoding system result from the facts that each pulse begins substantially immediately after the next preceding pulse and is of op¬ posite polarity with respect thereto. In a conventional pulse-width modulation system the pulses are transmitted periodically, and the period is fixed and long enough to accommodate the widest pulse to be transmitted; at the same time, the original signals to be sampled must be sampled at least as frequently as the shortest time for which the signal may stay at one value, since other- wise significant changes will be missed by the sampler.

In the system of the invention as applied to the time multiplexing of original parallel signals, each successive sampling pulse occurs promptly upon the end of the preceding encoded pulse, and the interval between sampling pulses therefore varies with changes in encoded pulse width. Accordingly, the inter-sample interval is maximum for the longest encoding pulse, and is shortest for the shortest encoding pulse. In a binary system where a 1 is represented by a shorter encoded pulse (e.g. 0.5 microsecond) and a 0 by an encoded pulse which is rela¬ tively long (e.g. 1 microsecond) , and where there are a plurality of parallel signals to be sampled in repeating order, the more short encoded pulses there are (the more l's relative to the number of 0's) the more the time be¬ tween successive samplings of the same signal is reduced. Such reductions in the sampling interval for each original signal make the system better able to handle rapid changes in the original signals with accuracy and reliability,

and hence permit a reduction in bandwidth of the trans¬ mission channel while maintaining the desired level of accuracy and reliability of information transmission.

In addition, by using successive encoded pulses of alternate polarities, the bandwidth required is further reduced, for reasons set forth hereinafter. This advantage exists even when the invention is not used to encode samples of parallel signals, but instead is used for the encoding of original serial signals.

Furthermore, in the preferred embodiment the input signals are classified into at least two groups according to the shortest time for which they may stay at a given level, the faster-changing group being desig¬ nated herein as high-priority (HP) signals and the more slowly changing group being designated herein as low- priority (LP) signals. The LP signals are repetitively sampled at a rate sufficient to provide accurate and reliable transmission of them, and the resultant samples are applied to the transmission channel in serial form, except when a change occurs in any of the HP signals.

Such change in any one of the group of HP signals is de¬ tected, the transmission of lower-priority signals im¬ mediately terminated, and the HP signals immediately sampled and transmitted through the common channel in serial form, in place of the LP signals which would other¬ wise be transmitted at that time. Preferably samples of the entire group of higher-priority signals are trans¬ mitted at such times. In the preferred embodiment, im¬ mediately following the end of the higher-priority trans- mission the sampling and transmission of the lower-priority signals is resumed substantially where it left off.

In this way the higher-priority signals are sampled and "put through" the transmission channel im¬ mediately upon a change in any of them, and the inter¬ rupted lower-priority signal transmission is thereafter promptly completed, rather than starting again at the beginning of the low-priority sampling cycle. The result is that the HP signals do not have to wait for the LP signals to be sampled before receiving attention from the sampler, and even with a relatively low sampling rate any changed level of the high-priority signals will be sampled before it can disappear. The system is therefore able to provides accurate and reliable information trans¬ mission with a transmission bandwidth less than would otherwise be necessary.

To permit proper use of the higher-priority

(HP) and lower-priority (LP) signal samples at the other end of the transmission channel, each group or "frame" corresponding to one complete sampling of the LP parallel signals, or of the HP parallel signals, is preferably identified as being an LP or an HP frame by means of identifying signals which are also transmitted through the channel. Preferably each of these identifying signals comprises a pulse of a first given duration preceding each LP frame and a pulse of a second, shorter duration preceding each HP frame. This enables the receiving ap¬ paratus at the far end of the channel to recognize whether an LP or an HP frame is being received, so it can process the two types of frames properly and deliver the trans¬ mitted samples to the appropriate storage locations for reconstituting the original parallel signals.

Further as to the preferred embodiment, the system at the input end of the transmission channel pre¬ ferably comprises electronic switch means which in a first

position normally causes LP signals to be supplied to the transmission channel but which is responsive to a change in any of said HP signals to be switched to its alternate position, in which it causes the HP signals to be supplied to the transmission line in place of the LP signals. Preferably this is accomplished by means of a sampling system which samples the parallel LP signals in a predetermined order, which is interrupted in response to a change in the HP signals but "remembers" where it leaves off in sampling the LP signals, which next samples each of the HP signals, and which then resumes sampling of the LP signals, unless a further change in the HP sig¬ nal occurs in which case it samples the HP signals again.

BRIEF DESCRIPTION OF FIGURES

These and other objects and features of the invention will become more apparent from a consideration of the following detailed description, taken in connec¬ tion with the accompanying drawings, in which:

Figure 1 is a block diagram illustrating one use of the invention:

Figure 2 is a perspective view, with parts bro¬ ken away, of a cable system embodying the invention in a presently-preferred form;

Figure 2A is an enlarged, fragmentary perspective view showing the construction of one of the types of cables shown in Figure 2;

Figure 2B is a similar view of the other type of cable shown in Figure 2;

Figure 3 is a block diagram of the electrical system used in the connector plug assemblies of Figure 2;

Figures 4-7 are graphical representations, to a common horizontal time scale, to which reference will be made in explaining the nature and certain advantages of the encoding system of the present invention;

Figure 8 is a block diagram of the electronic circuitry preferably employed in both of the cable con- nector plug assemblies to achieve parallel-to-serial con¬ version;

Figure 9 is a block diagram of the electronic circuitry preferably employed in both of the cable con¬ nector plug assemblies to achieve serial-to-parallel con- version;

Figures 10 and 11 are graphical representations showing waveforms with reference to which the typical nature of the information conveyed by the system will be described;

Figures 12 and 13 are graphical representations of various signals occurring in the MUX and DEMUX units of a preferred embodiment of the invention, respectively;

Figure 14 is a functional block diagram of a preferred form of input transition timer for use in the receiving portions of each cable connector plug assembly; and

Figure 15 is a series of timing diagrams or graphs, to the same time scale, illustrating the operation of the timer of Figure 14.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Referring to the specific embodiments of the invention shown in the figures by way of example only, and without thereby in any way limiting the scope of the invention. Figure 1 illustrates one communication system to which the invention is applicable. Here there is shown a data center 10 at which there is located a computer CPU 12 having front end processors FEP-1, FEP-2 and FEP- 3. Such front-end processors typically have from 16 to 64 or more ports to which modem cables may be connected. The purpose of the front-end processors is to relieve the host computer of the processing burden uniquely as¬ sociated with maintaining communications between elements of a data communications processor. The FEP's 1, 2 and 3 are provided with respective FEP female connector plug units 16, 18 and 20 mounted thereon, each containing multi¬ ple female connector members presenting parallel signals for transmission to associated modems (for example, MODEM 1, MODEM 2 and MODEM 3, respectively), and also having female connector members for receiving signals delivered to them from such modems. In a typical example, connect¬ or plug units 16, 18 and 20 and each of the other inter- unit connector plug units may have 25 connector members, as in the EIA Type RS-232-C connector. Male connector plug units 21, 22 and 23 contain connector members mating with the female connector members of plug units 16, 18 and 20 respectively.

Communication lines 24, 26 and 28, commonly referred to as data set cables, connect male connector plug units 21, 22 and 23 to male modem connector plug units 29, 30 and 31 which in turn are matable with cor¬ responding female connector plug units 32, 33 and 34 mounted

on respective modems 1, 2 and 3 to permit two-way transmis¬ sion of signals between the FEP's and the modems. The other ends of the modems are operatively connected to the adjacent ends of telephone company lines 36, 38 and 40 by conventional connectors, not shown.

More remote from the data center 10 is an office 38 containing, in this example, remote terminal 1, remote terminal 2 and remote terminal 3, which may be word pro¬ cessors, financial accounting computers, personal com- puters, etc. In this instance it is desired to connect the remote terminals for two-way communication with the CPU 12 by way of the telephone company lines 36, 38 and 40, the modems 1, 2 and 3 and the FEP's 1, 2 and 3 at the data center. This is accomplished by means of the modems lA, 2A and 3A at the office, and the data set cables 50, 52 and 54 provided at one of their ends with connector plug units 56, 58 and 60 and at their other ends with connector plug units 62, 64 and 66 , respectively, for plug-in connection with corresponding connector plug units on the modems 1A 2A and 3A and on remote terminals 1-3.

It will be understood that each of the modems shown may be at a substantial distance from its corres¬ ponding FEP or remote terminal, e.g. 100 to 1,000 feet.. This is primarily because the modems are usually located where the telephone company lines enter the building, which is normally at a substantial distance from the com¬ puter CPU and the remote terminals.

Further, it will be understood that usually, and in this example, the FEP's, modems and remote term- inals are designed to accept and utilize parallel digital signals presented to them on the various connectors shown.

which signals typically consist of data and clock pulses together with a substantial number of control and signal¬ ling pulses for establishing proper contact, lock-in and other functions.

In Figure 1 the data set cables and the connector plug units at each of their ends are shown only schematical¬ ly, and in a prior-art system each such cable would com¬ prise one conductor for each of the operative pins on the connectors. In the present example, this could in- volve a 25-conductor cable, if all pins are used; such cables are expensive, as well as bulky and difficult to place and dress in a convenient, unobtrusive manner. In one of its aspects, the present invention replaces such a multi-conductor cable with a much simpler commu- nication line, for example a cabling containing over most of its length only two twisted-pairs of wire, one pair transmitting serial signals in one direction and the other pair transmitting serial signals in the other direction. To enable this operation, each of the connector plug as- semblies secured to the opposite ends of each data set cable such as 24 preferably includes both a serial-to- parallel and a parallel-to-serial converter, whereby par¬ allel signals travelling in either direction will be placed upon the data set cable in serial form, and at the op- posite end of the line will be converted back to parallel.

Since all of the cables and connector plug as¬ semblies may be the same, only data set cable 24 and its connector assemblies will be described in detail. Phys¬ ically, the form of cable assembly of the invention which is shown in Figures 2, 2A and 2B is suitable for use be¬ tween each of the modems of Fig. 1 and its associated FEP or remote terminal, and in this example it will be

assumed that it is used for all modem connections. Nu¬ merals used in Figure 2 which correspond to those used in Figure 1 denote corresponding parts.

Referring then to Figs. 2, 2A and 2B, in this example the cable connector system comprises two iden¬ tical converter plug units 60 and 62, each comprising a connector pin portion such as 66 provided with a set of 25 male connector pins such as 68 mounted at one end of a generally rectangular metal or plastic plug housing 70 and adapted to plug into the connector plug units 16 and 32 on the FEP-1 and Modem-1. At the other ends of each of the units 60 and 62 is provided a set of 7 male connector members such as 74, adapted to mate with the corresponding 7 female connector members of female plugs 76 and 78 respectively. The plugs 76 ^' and 78 are connect¬ ed to 7-wire cables 80 and 82 respectively, shown in Fig. 2B, which are typically only a few feet long and provided at their other ends with seven-pin female plugs 83 and 84, respectively. These plugs are adapted to mate with male plug units 85 and 85A mounted on dc power supply units 86, 86A respectively. The latter power supply units are mounted adjacent the respective plug units 16 and 32. The power supply units are provided with ac line cords 87 and 87A terminating in ordinary ac wall plugs such as 88 for plugging into corresponding ac power-line sockets adjacent the equipment. Each of the power supply units contains a small ac power supply, with appropriate rectifying and filtering elements, for providing a rela¬ tively low dc voltage, for example 18 volts isolated from ground, to the converter plug units 60 and 62, wherein it may be adjusted to +9 and -9 volts.

Also provided on the power supply units are 5-ρin male connector plugs such as 88, matable with female 5-pin plugs 89,89A on the opposite ends of 4-wire cable 90. The latter cable contains the two twisted-pair lines, as shown in Figure 2A, which carry the serial multiplex¬ ed signals. A ground wire may optionally be included, and if used may be in the form of an outside cable shield. It is these two twisted-pair lines which are typically of substantial length, e.g. up to 1,000 feet, and present very substantial advantages in reduced expense and size as compared with multi-conductor lines of perhaps 25 con¬ ductors of the same length previously used for the same general purpose. Furthermore, such twisted-pair lines are often already in place in may buildings, having been previously used for other purposes, or installed for pos¬ sible future use, and use of such existing lines for cable 90 will ^' generally provide a substantial financial saving. In some cases a single twisted-pair line may be used be¬ tween the connectors of the connector plug assemblies, either when transmission is to be only in one direction or when the system permits the line to be used alternately for transmission in both directions. However, it is here preferred to utilize a separate line for each direction of transmission, within a single cable, and the invention will be described with particular reference to such em¬ bodiment.

It will be understood that, in use, one merely plugs each of the connector plugs 89 and 89A at the op¬ posite ends of the 4-wire cable 90 into the power supply plug receptacles such as 88, plugs each of the 7-wire cables into one of the power supply units and the associat¬ ed converter plug unit 60 or 62, and plugs the two ac line cords 87 and 87A into ac wall sockets adjacent each power supply unit. Inside the power supply units the

two twisted-pair lines of cable 90 are directly connected to the two twisted-pair lines in each of cables 80 and 82, to complete the two twisted-pair line extending from converter unit 60 to converter unit 62.

It will also be understood that in other embodi¬ ments the dc power for each converter unit may be provided completely independently of the signal cables, e.g. through the plug unit 16, in which case the two twisted-pair lines may extend directly from converter plug 60 to converter plug 62, rather than by way of the power supply units; or a "free-standing" power supply unit may be used, sup¬ ported only by the signal cable rather than being mounted to a frame.

Figure 3 illustrates broadly the electrical circuitry mounted within the case of each of the connector plug assemblies 60 and 62 of the cable connector system. For the present purposes it is assumed that the circuitry shown is that in the connector plug housing 70 of con¬ verter plug unit 60, which is plugged into connector plug receptacle 16. However, the same type of unit would be used in the converter plug unit 62 which is plugged into connector 32 of MODEM 1, and in all of the other converter plug units secured to all of the other cables shown in Figure 1.

In Fig. 3, it is assumed that the connector pin assembly 66 has 25 pins, two of which are used for data pulses and clock pulses to be delivered to Mode - 1 from FΞP-1, two of which are to receive data and clock pulses from Modem-1, one of which provides a frame ground, one of which provides a signal ground, two of which con¬ stitute + and - voltage test points, and the remaining 16 of which are for infrequently-changing control signals, used in both directions of transmission.

-1&-

DCE indicates that the signal is from the MODEM end (e.g. reaching converter .plug unit 60 from Modem-1) , and DTE indicates that the signal is from the CPU or from the remote terminal end (e.g. reaching converter 60 from CPU 12) . The signals on pins 21 and 23 in TABLE I can arrive from either direction, although most commonly from the MODEM end. The levels on pins 9 and 10 are not trans¬ mitted, and merely constitute test voltages which can be contacted with a probe when connector 21 is removed. The frame ground on pin 1 is not sampled but is dc-con- nected to ground, and the signal ground is not sampled but is used as a reference for the signals on converter plug unit 60.

Figures 10 and 11 show typical input signals applied to converter plug units 60 and 62, to illustrate the general magnitudes of the frequencies and time in¬ tervals typically involved, in this case for half-duplex operation.

In Figure 10 the signals named at the left ori- ginate at an FEP-1 of the CPU, while those named at the right originate at the Modem 1. In Fig. 10A there is shown a Data Terminal Ready signal, constituting a high level produced by the terminal when it is in a ready con¬ dition; this signal may persist all day, or for at least minutes at a time. At 10B is shown a Data Set Ready signal, originating at the CPU, which also is typically on for hours or at least minutes. Figure 10C shows a Request To Send signal from the terminal end, consisting here of two spaced-apart pulses each of a duration to encompass a useful block of data; Figure 10D shows two corresponding Clear To Send pulse signals from the MODEM end, only slight¬ ly delayed with respect to the Request To Send signal, each pulse being of comparable duration to the Request To Send pulses. As represented by the shaded area in

Figure 10E, the terminal equipment has been sending clock pulses continuously, at a high rate, as depicted in Fig. 11A, and a block of high-speed data is sent by the term¬ inal during the pulses shown in Fig. 10F, each such pulse starting after a Clear to Send pulse and ending at the end of the Request to Send Pulse; typical data are il¬ lustrated in Figure llB.

Figure 10G shows the Carrier Detect signal orig¬ inating at the Modem upon detection of data being sent from the remote Modem.

Figure 10H shows the Receive Clock signal orig¬ inating at the Modem and derived from the data being sent from the remote Modem.

Figure 101 shows the Receive Data signal orig- inating at the Modem and resulting from demodulation of the signal sent by the remote modem.

The binary data shown in Fig. llB are in stand¬ ard NRZ form and, during each associated clock pulse of Fig. 11A, represent the series of l's and 0's at the bot- torn of Fig. llB. This is the data contained in the en¬ velope of the signals of Fig. 10 indicated by diagonal lines.

The clock pulses of Fig. 11A define a clock rate, which is also the data bit rate, and which may typ- ically be anywhere from about 2,400 to 19,200 bits per second; thus a bit time may be as short as about 52 micro¬ seconds. Message lengths (data blocks of Fig. 10F) may vary from about 10 to 2,000 eight-bit characters, i.e. from 80 to about 16,000 bits. Assuming operation at the high-speed end of this ranges, a message of 16,000 bits

may be sent in a block having a duration of about 0.832 seconds, with each bit time having a duration of about 52 microseconds. The clock pulses, however, are then considerably shorter in duration than the bit interval, e.g. about half as long, or about 26 microseconds long with 26 microseconds between them. In order for the clock pulses from a terminal or CPU to be sampled and trans¬ mitted properly by the sampling systems of the multiplexers used in the present invention, and with the sampling oc- curring synchronously with respect to the clock pulses at for example an 8 KHz rate (125 microseconds per cycle of sampling of each of the 12 signals) , it is desirable to resample each input signal at least twice per system clock cycle, e.g. at least every 26 microseconds; this would merely assure sampling at least at the edges of a clock pulse, and td provide sampling which will assure accurate sensing of when each clock pulse starts and ends (the timing of its edges) , at least several samplings per half clock cycle are needed. In fact, the position of a clock pulse edge, or of a data signal transition, can only be detected with a time tolerance about equal to half the time interval at which it is resampled. Accord¬ ingly, if one wishes to represent the position of an edge of a 26 microseconds clock pulse with an accuracy of 6 microseconds one should sample at least every 6 micro¬ seconds with a very narrow sampling interval (fractions of a microsecond) .

As will presently be described, each of the more slowly or infrequently variable signals (i.e. all except the clock end data signals) is generally sampled at a relatively lower rate (at 8 to 14 microsecond in¬ tervals, depending on the values of the input signals being sampled) , and each of the more rapidly variable

signals (the data and clock signals) is generally trans¬ mitted with a shorter waiting-time (3.5 to 5.5 microsec¬ onds, depending on the values of the signals being sam¬ pled) .

Referring now to Figure 3, amplifiers 92 and

94 supply the separate parallel high-priority and low- priority signals, respectively, from plug 66 to a parallel- to-serial multiplexer 96, preferably provided on a semi¬ conductor chip 97 physically located within the plug hous- ing 70 of Fig. 2. The output of the multiplexer 96 is supplied through balanced-output driver amplifier 98 to twisted-pair wires 100. The latter twisted pair extends physically through cable 80, power supply units 86 and 86A and cable 90 of Fig. 2, to Modem-1. DC power from the power supply unit 86 is supplied over the two lines 101.

Conversely, serial digital information arriving from Modem-1 on twisted-pair wires 120 in cable 80 passes through the balanced-input receiver amplifiers 122, and the output of the latter amplifier is supplied to the serial-to-parallel demultiplexer 130 on chip 97. The reconstituted parallel HP information is supplied from demultiplexer 130 through amplifier 132 to appropriate pins of the connector plug 66, while the reconstituted parallel LP information from the demultiplexer is supplied by way of amplifier 134 to other appropriate pins of the same connector plug. It will be understood that each of the amplifier components 92, 94, 132 and 134 designated "A" actually includes a plurality of amplifier devices, as appropriate for their respective functions. Prefer¬ ably, a timing oscillator 140 is also provided on chip 97, the crystal stabilizing unit 142 for which is con¬ nected to the oscillator circuit on the chip but is mount¬ ed separately from the chip within the plug housing.

Figure 4 shows the pulse durations which are utilized in this embodiment to represent in serial form on twisted-pair wires 100 the parallel information pre¬ sented at connector plug 16 of FEP-1. As indicated at A in Fig. 4, a binary 1 is represented by two identical but oppositely poled 0.5 microsecond pulses, one on each of the wires of the twisted pair 100; as shown at B, a binary 0 is represented by two oppositely-poled 1 micro¬ second pulses; as represented at C, the "HP sync" pulse which identifies high-priority data -is represented by two oppositely-poled 1.5 microsecond pulses; and the "LP sync" pulse which identifies LP data is represented by oppositely-poled pulses 2 microseconds in duration, in this example.

Figure 5 illustrates a low-priority frame formed by the multiplexer 96, and Figure 6 illustrates a high- priority frame formed by that multiplexer. Referring to Fig. 5, the 2 microsecond initial pulse labelled "LP Sync" represents the pulse on the two-wire line which identifies the immediately subsequent data pulses as re¬ lating to an LP frame. The pulses labelled 1 through 12 represent, by their individual durations, the arbi¬ trarily chosen binary levels of a group of 12 original parallel LP signals supplied to the input of the multi- plexer, specifically in this example 110010111011. The frame is then repeated, with numbers of 0's and l's ap¬ propriate to the values of the original parallel low-prior¬ ity signals at that later time. The terminal half-micro¬ second portion of the LP sync pulse is cross-hatched to indicate a time interval near the end of the LP sync pulse during which the LP frame cannot be interrupted by an HP frame, for reasons described more fully hereinafter. Unused pins (or pins with constant levels) are not con¬ nected to the Mux at their source connector. At their destination connector, corresponding pins are connected

to either a + or - voltage from the cable multiplexer power supply. Pins on the cable Mux chip corresponding to unused bits within the multiplexed frame are tied to a + voltage from the cable multiplexer power supply so that they are sensed and transmitted as binary ones and therefore require a shorter transmission time.

Figure 6 shows the HP sync pulse of duration 1 microsecond followed by 4 data pulses each having a duration which depends upon whether the pulse is repre- senting a binary 1 or 0; in this example the frame is made up of HP bits 1, 2, 3 and 4 is assumed to represent binary digits 1, 0, 1 and 0, respectively.

The graphs of Figure 7 illustrate some of the advantages of the above-described -general type of pulse width encoding of information. At Fig. 7a there is shown a previously-known NRZ encoding of the binary digital information 110010111011. It utilizes 12 corresponding time slots or bit intervals of equal durations - in this example about 1 microsecond; a corresponding 1 MHz clock signal is shown at 7B. The bit rate is constant, and each bit interval contains a level which is either Low or High depending upon whether a 0 or 1 is represented. The total time for transmission of this information is therefore 12 microseconds.

In Fig. 7C there is illustrated a known ratio- coding system used to represent the same information. In this encoding system a 1 is represented within each 1 microsecond time slot by a High level which is longer than the Low level, while a 0 is represented by a Low level longer than the High level. Again, the bit rate is constant and 12 microseconds are required for the frame

At. Fig. 7D there is shown an encoding scheme ac¬ cording to a preferred form of the invention, designated as NRZD encoding, according to which each successive pulse be¬ gins substantially immediately upon termination of the pre- ceding pulse. Since in this example there are 8 binary l's and 4 binary 0's in the frame, there are 8 half-micro¬ second pulses and 4 one-microsecond pulse, the total time required to represent the information therefore being 8 microseconds. If all of the bits had been l's, the time to represent the information would be only 6 micro¬ seconds, or one-half the time required by the conventional encoding systems of Figs. 7A and 7C. If all pulses had been 0's, rather than l's, the time required to represent the information would be 12 microseconds, as in the prior- art systems; if the information is random (half l's and half 0's, on the average), the average time required will be 9 microseconds. In many systems it is known ahead of time that either 0's or l's will predominate, and by representing the more frequently-occurring binary value by the shorter pulse duration, the required time for a complete representation of the data will always be less than 8 microseconds, in the particular system under dis¬ cussion.

Fig. 7E shows the same encoding scheme as in Fig. 7D, but with the- levels reversed in polarity. For practical reasons it is preferred in the present embodi¬ ment to use both of the waveforms of these two figures, one on each of two twisted-pair wires, to give the dual balanced waveform depicted in Fig. 5.

An important advantage of the reduction in frame time provided by the invention is that where the pulses of different durations represent successive values of

a plurality of repetitively-sampled original signals, the shorter frame time resulting from the invention means that each of the original signals will be sampled more frequently than otherwise - that is, the frame can be refreshed more frequently, to give better representation of the information.

Figures 5 and 7D also illustrate another aspect of the preferred form of the invention, according to which the successive encoded pulses are provided with alternating polarities. The result of this is that the transmission band required to send the encoded signals with a given degree of distortion is only about half that which would be required for the signals of Figures 7A or 7C, for example. Ac¬ cordingly, in the above example, a transmission channel having a maximum modulation rate of 1 Mhz can transmit a steady stream of zeros at a 1 mbps rate, where each zero is represented by a 1 microsecond pulse and alternate - pulses are of opposite polarities. The same transmission channel can transfer equally well a steady stream of one's, each represented by a half-microsecond pulse, with every alternate pulse having an opposite polarity, at a 2 mbps rate. If the signal being transmitted averages half zeros and half ones, its effective transmission rate will be 1.5 mbps, which can be passed through a channel having a maximum modulation rate of 1.0 mbps without appreciable distortion. It has been found that in such a system of the invention one can provide reliable operation over about a 1000-foot length of good twisted-pair cable; if a lower maximum modulation rate of say 500,000 is used, good results can be obtained with a 3,000-4,000 foot cable.

It is noted that the encoding technique of the preferred form of the invention as depicted in Fig. 7D, for example, is also very easy to implement, since in essence

one need only provide a waveform which alternates between two fixed levels, and maintain it at each level for either one of two time intervals, depending upon whether the level is representing a 1 or a 0.

In the above discussion of Fig. 7, the effects of the LP and HP sync pulses have not been considered, since they are not necessary in all embodiments of the novel encoding system; their main function is to differ¬ entiate between HP and LP data when, as in the preferred embodiment, the input signals are classified and divided into HP and LP signals and processed differently. In other forms of the invention such classification and dif¬ ferentiation need not be employed, and although some form of synchronizing or timing may be desirable it can be accomplished in very different ways. However, in the preferred embodiment now being described, a complete LP frame includes an LP sync pulse as shown in Fig. 5, and a complete HP frame includes an HP sync pulse, thus adding 2 microseconds to the LP frame time and 1.5 microseconds to the HP frame time, giving frame times for the examples of Figs. 5 and 6 of from 8 to 14 microseconds for the LP frame and from 3.5 to 5.5 microseconds for the HP frame.

Figures 8 and 9 show further details of the preferred form of the multiplexer and demultiplexer sys- terns depicted more generally in Figure 3.

Referring first to Figure 8, there are shown 12 low-priority signal input lines 200 from the ampli¬ fiers 94 of Fig. 3, carrying the original, parallel, more- slowly variable LP signals. These input lines are con- nected to the signal input terminals of a 12-input scanner 202. In response to successive addresses supplied thereto over lines 204 from Mod-13 _. counter 206, the scanner 202

in effect connects successive ones of the input lines momentarily to the single output line 208 of the scanner. The scanner thus operates as a repetitive sampler of the 12 input signals thereto. In addition, the first, thir- teenth, twenty-fifth, etc. pulses from the Mod-13 counter are applied directly over LP sync line 212 to the output transition timer 214; these pulses constitute the timing source for the generation of the "LP Sync" signal by the output transition timer, which sync signal precedes and serves to identify the immediately following group or block of pulses as LP signals.

In the absence of high-priority information then, the LP input signals are sampled and the binary 1 and 0 samples passed serially through the normally-trans- missive NAND gate 220 and through OR gate 221 to the out¬ put transition timer 214; the digital data on the signal input line 213 of the transition timer are therefore in serial form, the successive pulses thereof indicating the corresponding levels of the parallel signals at the input to the scanner.

The output transition timer 214 responds to all of its input signals to produce on its output line 222 timing pulses which determine when transitions in the state of output toggle flip-flop 223 occur. 223 is a so-called D flip-flop which upon the occurrence of each leading edge of a timing pulse on line 222 assumes at its output line 224 a state (High or Low) opposite that of its D input on line 225. Accordingly, the output of flip-flop 223 executes a transition between its High and Low states each time a timing pulse on line 222 appears, and the time for which it remains in either state depends on the time between successive timing pulses. The output on line 224 is therefore the desired NRZD signal.

In the absence of changes in the HP signals, the output transition timer 214 first produces on its output line 222 a timing pulse which initiates the Low- Priority Sync pulse of 2 microseconds duration, followed by a timing pulse which terminates the sync pulse. The next timing pulse changes the state of the flip-flop 224 one-half or 1 microsecond later, depending upon whether a 1 or a 0 is to be represented.

The Mod-13 counter 206 is not free-running, but only advances its count to shift sampling to the next LP input signal in response to a clock pulse delivered to its clock input terminal 226 over line 228 from AND gate 230. One input terminal 232 of the latter gate is supplied with Advance signals from output transition timer 214, over Advance line 236. These Advance pulses are the same as the timing pulses on line 222, and are denoted as Advance pulses to facilitate easy comprehension of their functions. Accordingly, each Advance pulse occurs at a transition in the output NRZD signal, and serves to shift the scanner to the next LP input signal, to pro¬ duce a binary sample "telling" the output transition timer whether to wait 1 or 0.5 microseconds before producing the next timing pulse. The other input to the AND gate 230 is supplied over output line 240 from the High-Prior- ity, Low-Priority Frame Flip-Flop (HP/LP FR FF) 242, which in its normal state supplies to AND gate 230 a level which renders it transmissive and permits the Advance signals to pass through the AND gate 230 and to advance the Mod- 13 counter, during transmissions of LP signals.

Considering now the circuitry shown in Fig.

8 for accomplishing special handling of the HP signals, the four high-priority information input lines 246 carry¬ ing the parallel HP signals are supplied both to the sig¬ nal input terminals of a conventional four-input scanner

250, operative when activated to sample the HP signals, and to a conventional level-change detector 252 for sens¬ ing when a change occurs in any of the four input signals. Normally, during the transmission of low-priority signals, the four-input scanner is not activated and produces no output. However, when one of the four HP signals changes level, this change in level is detected by the level change detector 252, which may be a device ^' of known form which, in effect, merely stores the most recent levels of the four signals and then compares each of them with its next subsequent value to detect any changes therein. Upon such detection of a change of level of any of the four signals, the output of detector 252 changes to its op¬ posite state. The latter change in level passes through normally-transmissive NAND gate 260, the control term¬ inal 262 of which is connected to an END OF LP SYNC line 266 which normally permits this to occur. The resultant change in level at the Set input 270 of the HP/LP FR FF 242 causes it to switch immediately to its opposite state, in which its output line 240, denoted LP FRAME, goes Low and its other output line 272 (marked HP FRAME) goes High. This change on line 240 makes AND gate 230 nonresponsive to the Advance pulses so as to terminate the LP signal sampling by scanner 202, and renders NAND gate 220 non- transmissive so that the output of scanner 202 is isolated from the output transition timer 214; at the same time, the change on line 272 renders NAND gate 280 transmissive of the Advance pulses applied to it over line 236, and the latter Advance pulses are thereby applied over line 281 to the Mod-5 counter 282 to operate it through one cycle of five counts and to step the scanner 250 through its five positions, after which HP/LP FR FF 242 reverts to its normal state and supplies a signal to the reset terminal RST of level change detector 252 to reset it.

Accordingly, during the Mod-5 count, in response to the next Advance pulse, Mσd-5 counter 282 puts out on line 283 a High-Priority Sync timing pulse for appli¬ cation to output transition timer 214, which responds by holding flip-flop 223 in whatever state it is in for 1.5 microseconds, to form the NRZD HP Sync pulse; at the end of this sync pulse the next Advance pulse is applied over Advance line 236 through AND gate 280 to the Mod- 5 counter to produce the first address signal in the 4- input scanner 250 and thereby sample the first HP input signal. This sample passes through NAND gate 284 (nor¬ mally non-transmissive, but rendered transmissive by the HP FRAME signal on line 272) and OR gate 221 to the output transition timer 214, which causes the timer 214 to pro- duce a half or a one microsecond pulse at the NRZD output line 224 depending on the sample. At the end of this output pulse, the next Advance pulse is generated and advances the Mod-5 counter by one count and the input scanner to its 'next address-, analogously to the operation of Mod-13 counter.

In this way the information on the four high- priority input lines is encoded on the NRZD output line 224 in the form of successive pulses of alternating po¬ larity, one immediately following the other, and with either half-microsecond or one-microsecond durations de¬ pending upon whether they are representing a 1 or a 0. If no further level change occurs in any of the HP sig¬ nals, there is no further output from the previously-reset level change detector 252, and the HP/LP FR FF reverts to its normal state in response to the END OF HP FRAME signal produced on line 290 by the end of counting in Mod-5 counter 282. In response to the reversion of the HP/LP FR FF 242 to its normal state, the Mod-13 counter

resu es its counting at the point where it left off, thus causing scanner 202 to complete its sampling of the LP frame.

The above-mentioned END OF LP SYNC line 266 5 is normally supplied by the output transition timer 214 with a level which maintains the NAND gate 260 in its transmissive condition. However, during the latter part of each low-priority frame sync pulse, represented by the shaded area in Fig. 5, the output transition timer

10 produces a level on line 266 which renders NAND gate 260 non-transmissive during such time. Accordingly, if a level change detector pulse occurs in this time interval the LP scanner 202 will nevertheless continue to operate until the end of the LP sync pulse, at which time a change in

15. level on line 266 renders NAND gate 260 transmissive a- gain, and the high-priority frame will begin. The dura¬ tion of this period of non-interruptability of the LP sampling is in this example about one-half microsecond, so that the maximum time required to produce an HP sample

20 is increased in such event by a half microsecond, to a total of from about 4 microseconds to about 6 microseconds.

It is noted that, with the exception of this time interval near the end of the LP sync pulse, the high- priority frame may inject itself into the low-priority 25 frame at any time, even during the LP frame Sync Pulse and even during one of the LP binary data-representing pulses of one-half or one microsecond normal duration. This will be more fully appreciated from the discussion hereinafter of the timing diagrams of Figs. 10 and 11.

30 Internal clock timing for the multiplexer is provided by a clock oscillator 292.

The NRZD output of output toggle flip-flop 223 in this example is passed through balanced driver 98 of Figure 3 to the twisted-pair line 100, whereby two such NRZD signals of respectively opposite polarities are placed on the two wires, as described previously.

A demultiplexer corresponding to the demulti¬ plexer of Fig. 3, and usable with the multiplexer of Fig¬ ure 8, is shown in Figure 9. In Figure 9 the double-ended balanced pair of signals on line 120 of Fig. 3 have been passed through the balanced receiver amplifier 122 of

Fig. 3 to NRZD input line 300, which conveys them to the signal input of input transition timer 303, clocked in response to timing provided by an asynchronous oscillator 301. Transition timer 303 senses the time of occurrence of each transition in the level of the received signal, and measures the times between successive transitions. After so doing, it applies a pulse to HP SYNC line 304 upon reception of a 1.5 microsecond pulse, applies a pulse to LP SYNC line 306 upon reception of a 2 microsecond pulse, applies a narrow pulse to transition clock line

308 whenever a data-representing transition in level occurs in the received signal and, when data pulses are received representing the original multiplexer input signals to MUX 96 of Fig. 3, applies data levels to data line 310 representing l's or 0's depending upon whether the received data pulses are 0.5 or 1 microsecond in duration. It is understood that for purposes of the present discussion the data pulses at the DEMUX represent both original "data" signals and original "clock" input signals to the remote MUX, and that the transition clock constitutes narrow periodic timing pulses coincident with the occurrence of transitions in the level of the received NRZD signals (See Fig. 13B) .

The data line 310 is connected to the data input terminals of a 4-bit output register 312 and of a 12-bit output register 314 over lines 311 and 311A respectively, the register 312 being used to reconstitute and store the high-priority information and the register 314 to reconstitute and store the low-priority information. Each of these registers is provided with an IN EN term¬ inal, supplied from the respective Enable lines 324 and 326, and effective to permit registering of data from the data line only when the corresponding Enable line is high. The transtion clock pulses are applied to the clock input terminals of the 4- and 12-bit registers, while the LP SYNC pulses are applied to the RESET term¬ inals of Mod-13 counter 330 and the HP SYNC pulses are applied to the set terminal of an HP/LP FRAME FLIP-FLOP 331.

More particularly, during the reception of an LP frame the Mod-13 counter 330 is reset by the pulse supplied to its reset terminal over the LP SYNC line 306. When enabled and clocked, Mod-13 counter 330 then operates over address lines 340, in a conventional manner, to suc¬ cessively address register locations in the 12-bit output register 314, so that the serial data applied to the re¬ gister over data line 311A will be strobed into appro- priate parallel locations therein. In order to time the changes in address and the strobing of the data in ac¬ cordance with the aperiodic received data, Mod-13 counter 330 is advanced in response to the transition clock pulses which are supplied to its clock terminal 344 over line 346 by way of AND gate 348 so long as LP FRAME line 326 is High to render the AND gate transmissive of the transi¬ tion clock pulses.

The enabled states of the Mod-13 counter 330 and of the 12-bit output register 314 are both controlled over LP FRAME line 326 by one output of the High-Priority, Low-Priority Frame Flip-Flop 331 (HP/LP FR FF) , which in its reset state enables both the Mod-13 counter and the 12-bit output register. So long as low-priority sig¬ nals are being received, parallel signal levels on the 12 low-priority output lines 366 of the output register 314 will therefore comprise the desired reconstituted parallel binary information for direct supply in parallel form to Modem-1 (Fig. 1). So long as no HP signals are received, this operation continues.

When a high-priority frame is received by the input transition timer 303, the resultant HP SYNC pulse on line 304 shifts the HP/LP FR FF 331 to its opposite or set state, and resets Mod-5 counter 390 to its ini¬ tialized state in which it is ready to count in response to transition clock pulses. This change of state of flip- flop 331 acts over line 326 to disable the 12-bit- output register and, through the action of AND gate 348, imme¬ diately prevents further counting by the Mod-13 counter. Accordingly, all changes in the output of the 12-bit out¬ put register are arrested, and counting by the Mod-13 counter is immediately terminated.

At the same time, the Mod-5 counter 390 begins counting in response to transition clock pulses applied to it through AND gate 392 over lines 308 and 394. During the preceding low-priority signal interval the AND gate 392 was held non-transmissive by the level on the HP FRAME output line 396 of flip-flop 331, applied to one of its input terminals, which level simultaneously held disabled the 4-bit output register 312 over line 324, preventing

the registering of any new information in the latter reg¬ ister during low-priority frames. However, as mentioned above, the flipping of the flip-flop 331 to its Set state enables the 4-bit output register and also permits the transition clock pulses to be supplied to the Mod-5 count¬ er to produce the desired counting. Upon each count, the address lines 398 cause 4-bit output register 312 to advance its address, so that the data supplied to the latter register over line 310 are strobed into and reg- istered at the proper addresses, available for parallel output on HP output lines 399.

At the end of the 4 count by the Mod-5 counter, a fifth count produces an overflow output, supplied over reset line 400 to reset the HP/LP FR FF 331 to its "low- priority" state, whereby the Mod-13 counter immediately resumes its count and completes the reconstitution of the low-priority information at LP output lines 366, and the Mod-5 counter and 4-bit output register are disenabled by the HP FRAME signal on line 396.

Accordingly, the original parallel input signals at the input to the multiplexer system of Figure 8 are transformed into serial form, delivered over the two-wire transmission line to Modem-1 and, at the input of that modem, transferred back to parallel by the demultiplexer of Figure 9, with any new high-priority information in¬ jected by interrupting the transmission of the low-prior¬ ity information immediately, whenever changes in the high- priority information occur, and with the transmission of the LP information resumed immediately upon the absence of further changes in HP information. The same action occurs for signals travelling in the opposite direction, from Modem-1 to FEP-1.

Further details of the timing involved in the operations of this multiplexer and demultiplexer will be more fully understood from the timing diagrams of Fig¬ ures 12 and 13, in which time increases toward the right of the diagrams.

Referring first to Fig. 12, which relates to operation of the MUX of Fig. 8, at A there is shown the signal produced on LP FRAME line 240 by the HP/LP FR FF 242. In this example it is assumed that an LP frame was underway during the Low portion of the signal at Fig. 12A, was interrupted while the signal at Fig. 12A was High to enable an HP frame to be inserted, and then became Low again to permit the sampling and transmission of the LP signals to be resumed and completed.

At Fig. 12B is shown the relative timing of succes¬ sive samplings by the Mod-13 counter 206, in this case for 12 parallel input levels of 1101001001010. The times between samplings are one-half or one microsecond depend¬ ing on whether a 1 or 0 is represented.

In this example the HP frame begins just before the 6th count interval is complete, and the HP frame con¬ sisting of an HP SYNC pulse (Fig. 12E) and the four bits 1010 (Fig. 12C) is inserted. Upon termination of the HP frame, the Mod-13 counter begins to operate again, starting with and completing its 6th count interval and continuing with counts 7-12 as if it had not been interrupted. It is noted that when the HP SYNC pulse occurs, its effect is to extend the LP count interval then underway into the HP SYNC pulse, i.e. lengthen it to 1.5 microseconds. This eliminates the portion of the 6th LP count interval already timed- out, so that when the LP count resumes it begins at the start of the 6th count interval and a small amount of time

is thereby added to the LP frame time. Significantly, however, the desired prompt sampling of the HP input sig¬ nals is thereby accelerated, since the HP SYNC pulse is produced and the HP frame completed earlier than would otherwise be the case.

At Fig. 12F is shown the serial data (1/0), name¬ ly the levels of the samples of the parallel input signals, appearing at line 213 of Fig. 8; the shaded areas are not true data and are irrelevant.

At Fig. 12G are shown the Advance (transition) pulses, which are spaced apart by 1 or a half microsecond depending on whether a 0 or a 1 was sampled. The corre¬ sponding NRZD output produced on twisted-pair line 100 of Fig. 8 is shown at Fig. 12H, and. the bit numbers of the LP and HP frames are shown at Fig.. 121.

Fig. 13 shows corresponding waveforms which will occur in the DEMUX of Fig. 9 for the same data content as in Fig. 8. At A there are shown the NRZD input signals delivered over twisted-wire pair input line 300 of Input Transition Timer 303. It will be understood that actually the DEMUX to which MUX 96 of Fig. 3 would supply its serial output would be in the connector plug 29 of Fig. 1, not the DEMUX in the same connector plug as that in which the MUX 96 is located. However, since all MUX's and DEMUX's in the system are the same in this example, the operation will be described as if the DEMUX 130 were supplied with the output of MUX 96.

Returning to Fig. 13, at B are shown the transi¬ tion clock pulses, each produced on line 308 by timer 303 (Fig. 9) in response to a transition in level of the input NRZD signal on line 300; these are the transition pulses

which, used as clock pulses, strobe the data pulses into the proper flip-flop storage devices in the 4-bit and 12- bit output registers, while also being applied to the AND gates 348 and 392 to shift the counting between the Mod- 5 and Mσd-13 counters at the proper times.

At Figs 13C and 13D are shown the LP SYNC pulses and the HP SYNC pulses, produced by input transition timer 303 on lines 306 and 304, respectively. During an LP frame the LP SYNC resets the Mod-13 counter 330 to achieve syn- chronization between MUX and DEMUX, while the HP SYNC re¬ sets the Mod-5 counter 390 to synchronize it.

The data pulses shown at Fig. 13E are produced by the input transition timer, which measures the times between successive transitions in the received data signals and puts out onto line 310 a 1 or a 0 level depending on whether the received data pulse has a duration of 0.5 or 1 microsecond.

The counting by the Mod-5 counter is started and stopped by the changes of state of the HP/LP FR FF 331 shown at Fig. 13F.

Fig. 13G shows the overflow pulse which is ap¬ plied over line 400 from the Mod-5 counter to HP/LP FR FF 331 to reset it after all four of the HP pulses have been received and stored in the 4-bit output register.

Figs. 13H and 131 show the timing of the count by the Mod-5 and Mod-13 counters 390 and 330, the Mod-13 count being started by the LP SYNC pulse of 13C and in¬ terrupted by the HS SYNC pulse of Fig. 13D, and resuming its count after four counts by the Mod-5 counter.

Referring now in more detail to the nature and operations of the output transition timer 214 of Fig. 8 and the input transition timer of Fig. 9, it will be ap¬ preciated that, in performing the operations described above, output transition timer 214 is supplied with an LP SYNC pulse (Fig. 12D) over line 212, with an HP SYNC pulse (Fig. 12E) over line 283 and with 1/0, High-Low data levels (Fig. 12F) from line 213. In response to each LP SYNC pulse, it puts out an Advance pulse 2 microseconds after the immediately-preceding Advance pulse, and 1.5 microseconds after the immediately-preceding pulses it generates a 0.5 microsecond END OF LP SYNC pulse which is applied to line 266 to prevent change of state of HP/LP FR FF 242 and thus prevent interruption of the LP signal processing during the latter part of each LP SYNC pulse. In response to an HP SYNC pulse, it puts out an Advance pulse 1.5 microseconds after the last-previous Advance pulse, and in response to each data pulse it produces an Advance pulse either 1 or 0.5 microseconds after the pre- ceding pulse depending on the data content. Such a transi¬ tion timer which in essence merely puts out a pulse delayed by one of four possible delays, depending on the input signal supplied to it, can take any of a large variety of forms which will occur to one skilled in the art, in view of the present disclosure. Accordingly, no further more detailed disclosure thereof is set forth herein.

As examples only, one can use shift registers, tapped delay lines or counters for such purposes. It is presently preferred to use for this purpose a ripple count- er, since it is readily implemented on a custom integrated circuit chip.

The input transition timer 303 of Fig. 9 responds to the received NRZD signal on line 300 to produce the four output signals on output lines 304, 306, 308 and 310 described above with reference to Fig. 9. Again, this function also can be implemented in many different ways. It is presently preferred to use a transition detector which puts out a pulse (transition clock) each time the input signal executes a transition in either direction and then measures the time between transitions to put out an HP SYNC pulse, an LP SYNC pulse, a data High level or a data Low level, depending on the measured time between transition pulses. In order to accommodate distortion along the signal path between MUX and DEMUX, allowance is preferably made for some variation from ideal in the time between transitions. Thus a 1 is detected for an inter-transition time interval anywhere between 1/4 and 3/4 microseconds, a 0 for a time interval between 3/4 and 1 1/4 microseconds, an HP SYNC for a time interval between 1 1/4 and 1 3/4 microseconds, and an LP SYNC for a time interval between 1 3/4 and 2 1/4 microseconds. Further, in order to minimize false triggering on electrical noise signals, a blanking pulse suppressing all received signals for 1/4 microsecond following each valid received pulse is preferably used; moreover, a time-out Error signal is preferably generated and may be used to produce a display indication whenever a transition is not detected within 2.25 microseconds after a valid transition pulse. Since the master oscillator 301 preferably operates at 8 MHz and all timing is accurate to within one-half cycle of the local clock signal controlled by the oscillator, the time intervals mentioned above are typically accurate to within about - 31.25 nanoseconds.

One simple way in which the time between transi¬ tions can be measured is to use each transition pulse as a reference pulse to generate five different gate pulses, each starting progressively longer after the reference pulse and each lasting throughout the maximum frame time. The five gate pulses may be applied to respective different gate devices and the transition pulses applied to all five gates in parallel. A following transition pulse corre¬ sponding to the half-microsecond interval representing a 1 will pass through only the first gate, a transition pulse corresponding to a 0 will pass through only the first and second gates; a transition pulse corresponding to an HP sync pulse will pass through only the first three gates, and a transition pulse corresponding to an LP sync pulse will pass through only the first four of the gates. A pulse passing through all five gates will indicate an error, since it is beyond the maximum expected delay for a valid pulse. A simple logic circuit can then detect the delay of each transition pulse compared to the preceding transi- tion pulse by sensing whether outputs are obtained from 1, 2, 3 or 4 of the gates, and an error can be detected by sensing outputs from all five gates.

However, it is presently preferred to use the type of input transition timer shown in Figure 14, the operation of which is represented by the graphs of Figure 15.

Referring to the latter figures, the NRZD input line 300, the timing clock oscillator 301, and the output lines 304, 306, 308 and 310 for the HP SYNC, LP SYNC, Tran- sition Clock and Data 1/0, respectively, are as shown in Figure 9; the remainder of Fig. 15 shows functionally one form of electronics preferably used inside the input tran¬ sition timer 303.

In this form of the system, the input NRZD signal is applied to the edge detector 700, which also receives clock pulses from clock oscillator 301. It will be re¬ called that the data input signal to the edge detector is preferably bipolar in the sense that the signals on the two wires of the twisted-pair line are the same but of opposite polarities. Accordingly the edge detector, which may be conventional, preferably includes two edge- detecting flip-flops, one for each wire, and an inverter through which the signal from one of the wires is passed prior to its application to its edge-detecting flip-flop. The outputs of the two edge-detecting flip-flops may then be combined by applying them to the two input terminals of an OR gate, the output of the OR gate constituting the edge or transition pulses on line 702 which are applied to timing generator 704. One such edge pulse is produced for each positive or negative going transition in level of the received signal. Timing generator 704 responds to each such edge pulse to produce a series of three suc- σessive timing pulses ETl, ET2 and ET3.

Referring to Figure 15, at A there is shown the NRZD signal on input lead 301, including a reference edge and four successive edges following the reference edge by time intervals representing a 1, a 0, an HP SYNC pulse and an LP SYNC pulse. The other graphs of Fig. 15 are shown as they would exist if no succeeding edge were re¬ ceived. It will be understood that when a succeeding edge corresponding to a 1, a 0, an HP SYNC pulse or an LP SYNC pulse is received, the various graphs of Fig. 15 will re- vert promptly to the values shown for the reference pulse.

Fig. 15B shows the 8 MHz clock pulses from os¬ cillator 301 on the line marked "OSC (8MHz)".

At Fig. 15C there is identified by the diagonal hatching the oscillator cycle during which the reference transition occurs. It is at the first upward-going edge of the clock pulse following the reference edge pulse that the first timing pulse ETl is initiated, as shown at Fig. 15E. At Fig. 15D is shown an edge-detector inhibit pulse by which the edge-detector is preferably prevented from responding to received information for about 3/16 micro¬ second after the reference transition, to minimize inter- ference from electrical noise at such times.

As shown at Fig. 15E, ETl has a duration of 1/8 microsecond, and at its end the ET2 pulse is initiated by the timing generator, as shown at Fig. 15F. The ET2 pulse lasts for 1/16 microsecond, and at its end the ET3 pulses are initiated by the timing generator, as shown at Fig. 15G. The ET2 pulse is applied over line 720 to reset the edge detector promptly, preparing it to detect the next transition or pulse edge, and is also supplied through AND gate 722 to serve as the transition clock pulse on line 308 as described later herein.

The ET3 pulses are applied to the reset terminals of duration counter 726 and of decode flip-flops 728, over line 739; each of the latter devices operates continuously, and is reset upon the occurrence of each ET3 pulse.

Counter 726 of Figure 14 may constitute a chain of three individual counters producing respective outputs DC0, DC1 and DC2 as shown in Figs. 15H, I and J respect¬ ively. The DC0 constitutes a Low level initiated at the leading edge of the ET3 pulse and lasting 1/4 microsecond followed by a High level which lasts for 1/2 microsecond; this alternating of levels repeats until a subsequent edge

pulse occurs. As in others of the graphs, a double level indicates that the signal may have either level at such times.

As shown in Fig. 151, the first DC1 High level is also initiated at the leading edge of the ET3 pulse, and terminates after 1/2 microsecond; it then assumes its Low level for 1/4 microsecond, and this alternation of levels continues until the next edge pulse occurs.

As shown at Fig. 15J, the DC2 signal assumes a Low level at the beginning of the ET3 pulse, returns to its High level after 1/8 microsecond, and remains in its High state for 1/8 microsecond. Accordingly, it con¬ stitutes a square wave with a 1/4 microsecond periodicity.

The decode flip-flops 728 produce four outputs designated 2T, 3T, 4T and 5T on lines 732, 734, 736 and 738 respectively.

As shown at Fig. 15K, the 2T signal goes Low at the beginning of the first ETl pulse, stays Low for 1/2 microsecond, and then returns to its High state; it remains in its High state until the next transition occurs.

The 3T signal shown at Fig. 15L goes Low at the end of the ET3 pulse, remains Low for 1 microsecond, and then returns to its High Level; it then remains High until the next transition pulse.

The 4T signal shown at Fig. 15M goes Low at the beginning of ET3 and remains Low for 1 1/2 microseconds, after which it returns to its High level where it stays until the next transition pulse.

The 5T "Timeout Error" signal shown at Fig. 15N assumes a constant Low level at the beginning of ET3 and stays at this level for 2 microseconds. If there is no subsequent transition pulse until after this time, the 5T signal produces a High, indicating a malfunction. This signal may be used to change the condition of illumina¬ tion of a warning light, for example, when an error is thus detected.

It is also noted that, at the end of the ET2 pulse, the phase of the clock pulse timer is shifted by one-half cycle so that its rising edge is substantially coincident with the rising edge of the ET3 pulse. This is to assure that the timing discussed above will be ob¬ tained, in proper relation to the clock pulses, and is accomplished by the oscillator phase control 730 in re¬ sponse to the ET2 pulse supplied to it over line 731.

In operation, following each transition in the received pulses the duration counter and the decode flip- flops are reset and the timing generator started. Ini- tially, 2T holds the data line 732 High, indicating a 1, and the 3T and 4T signals hold the HP SYNC and LP SYNC lines 736 and 734 also High. As the duration counter counts upwardly, the Inhibit level is removed so that the next transition can be detected; next, the data line 732 (see 2T) goes Low for 1/2 microsecond, as shown in Fig. 15; if the next edge pulse occurs during this interval (as does the "1" edge signal shown in Fig. 15A) , then a 1 is indicated on the output line 310 of flip-flop 800 upon the occurrence of the next transition clock pulse on line 721, and the system is reset. If instead such next edge pulse following the reference edge pulse occurs in the next subsequent half-microsecond (as does the "0"

edge interval in Fig. 15A) , the 2T output on line 732 will have become High and flip-flop 800 will indicate a 0 on its output line 310 upon the occurrence of the next tran¬ sition clock pulse.

If instead the next transition pulse following the reference pulse occurs in the second-subsequent 1/2 microsecond interval corresponding to the HP SYNC interval in Fig. 15A, the 3T signal on line 734 will have become High while the 4T level on line 736 remains Low, as shown in Fig. 15; the 4T level is passed through the inverter 820 so that it is presented as a High to AND gate 822, the other 3T input to which, delivered over line 830, is also High. Accordingly, upon the occurrence of a subse¬ quent transition pulse in the 1 1/4 to 1 3/4 range of re- ceived pulse widths, flip-flop 832 is set, and reset short¬ ly thereafter by the ET3 level on line 834, to form on line 304 the pulse designated as HP SYNC.

If instead the first edge pulse following the reference edge pulse occurs in the delay interval 1 3/4 to 2 1/4 microseconds, the 3T level will have become High but the 4T level will be Low, as shown. The Low level of 3T serves to block AND gate 822, so that the HP SYNC pulse is not produced, while the High level of the 4T sig¬ nal is supplied over line 840 to set flip-flop 842; re- setting of flip-flop 842 by the ET3 signal on line 834 then produces the desired LP SYNC pulse on line 306.

Figure 15 0 shows the successive "windows" for reseption of the edge pulses, while Figure 15P shows the time durations of these windows.

It is noted that the transition pulse on line 720A is passed through an AND gate 722, the other input to which is supplied over line 910 from NOR gate 912. The NOR gate inputs are supplied by the 3T and 4T outputs of the Decode Flip-Flop 728, and when both of the latter signals are Low the NOR gate output is High and AND gate 722 transmits the transition clock pulse during the initial 1 3/4 microseconds interval following the reference pulse, during which it is receptive to 1 or 0 data pulses; for reception of the later sync-edge pulses, the NOR gate is blocked by the occurrence of a High 3T or 4T level which prevents registering of 1 and 0 signals at such times, as desired.

For simplicity and clarity of exposition of the general operation of the preferred input transition. Fig.

15 shows the leading edge of the ETl pulse as substantially coincident with the change in state of the "T" decode flip- flops, with the changes in state of the decode flip-flops and with the limits of the "windows" shown at Fig. 15P which define whether the edge pulse is interpreted as a 1, a 0, an HP SYNC or an LP SYNC pulse. Accordingly, it may not be entirely clear whether a correct interpretation will be made of an edge pulse which occurs very close to an extreme of one of those windows.

In actuality, various of the last-described sig¬ nals are caused by others of the signals, and hence they are not all exactly coincident in time. More particularly, the leading edge of the ETl pulse is applied to sense the states of the flip-flops 800, 832 and 842 which define the extremes of the "windows"; the changes in state of these decode or T flip-flops are actually caused by changes in state in the duration counter 726. Since the resultant

delay between the rising edges of the clock pulses applied to count the duration counter and the occurrence of the resultant changes in the states of the "T" flip-flops is greater than the delay between the clock pulses and the leading edges of the ETl pulses which strobe the Data,

HP SYNC and LP SYNC flip-flops, the edge pulses will cause reading of the latter flip-flops while they still retain the appropriate states to produce a proper interpretation of the transition or edge.

There are many other conventional arrangements for accomplishing the same purpose of forming a pulse of a particular polarity on a particular one of several lines depending on the delay of an input pulse with respect to a reference pulse.

There has therefore been described an encoding system in which a signal is generated which varies sub¬ stantially instantaneously between two different values and remains at each value for a time representative of the information then being encoded, with resultant advan- tages in the bandwidth required in the transmission chan¬ nel for the encoded signal, for a given level of system performance. The encoded information is detected at a receiver by measuring the time intervals between successive transitions in the encoded signal. Preferably the two different values are fixed amplitude levels, and the in¬ formation is binary, encoded as one of two different time intervals between transitions. Advantageously the encoding system is used in combination with apparatus which gives priority, in sampling and transmitting, to information which is more rapidly variable than the information encoded and sampled at other times. The system is especially well adapted for use in a system using a cable having a con¬ nector plug assembly at each end for effectively connecting

a set of input connectors carrying parallel signals to another set of output connectors, the present system serv¬ ing to encode the information in serial form at the. input end of the cable and to convert it back to parallel form at the output end of the cable.

While having certain definite advantages when used in a system using sampling, the invention is also applicable to systems which do not involve sampling, and in which in accordance with the invention, the information is nevertheless represented by the durations of immediately successive different signal levels; such systems are within the contemplated scope of the present invention.

There has also been provided a system in which sequential transmission of samples of a plurality of separate more slowly variable signals is automatically interrupted, whenever a change occurs in any of a plurality of more rapidly variable signals, to transmit the more-rapidly variable signals instead, after which the transmission of the more slowly variable signals is resumed where it was discontinued, with resultant saving in required trans¬ mission bandwidth. The system is particularly advantageous when used in a system in which the significant samples are encoded as pulses of alternating polarity, each pulse having a duration depending on the value of the signal sample which it represents, and with the pulses representing the more slowly variable original signals being accompanied by an identifying pulse of a characteristic width and the pulses representing the more rapidly varying original singals being accompanied by an identifying pulse of a different characteristic width.

Thus although the invention has been described with respect to specific embodiments in the interest of complete definiteness, it will be understood that it may be embodied in a variety of forms differing substantially from those shown and described, without departing from the spirit and scope of the invention as defined by the appended claims.