Title:
METHOD AND APPARATUS FOR ESTIMATING SIGNAL RELATED DELAYS IN A PLD DESIGN
Document Type and Number:
WIPO Patent Application WO/2022/245607
Kind Code:
A3
Abstract:
A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.
Inventors:
GREENE JONATHAN W (US)
BARAJAS GABRIEL (US)
LI FEI (US)
HASSAN HASSAN (CA)
TANDON JAMES SUMIT (US)
BARAJAS GABRIEL (US)
LI FEI (US)
HASSAN HASSAN (CA)
TANDON JAMES SUMIT (US)
Application Number:
PCT/US2022/028744
Publication Date:
January 12, 2023
Filing Date:
May 11, 2022
Export Citation:
Assignee:
MICROCHIP TECH INC (US)
International Classes:
G06F30/367; G06F119/12
Other References:
MYEONG-EUN HWANG ET AL: "Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE, US, vol. 56, no. 7, 1 July 2009 (2009-07-01), pages 1428 - 1441, XP011280499, ISSN: 1549-8328, DOI: 10.1109/TCSI.2008.2006217
Attorney, Agent or Firm:
GLASS, Kenneth (US)
Download PDF: