The invention relates to a method and apparatus for detection of a short circuit at a gate-controlled power switch, in par ticular a silicon carbide or a gallium nitride MOSFET.

There are different kinds of conventional detection methods for detection of a short circuit at a gate-controlled power switch.

With a conventional saturation detection method, the drain source voltage between the drain and source terminal of the MOSFET is sensed through a diode. When the sensed drain volt age is not dropping to its saturation voltage during the turn-on transient, a failure can be detected. This detection requires a relative careful design, and is highly tempera ture-dependent. It also requires saturation in case of MOSFETs and desaturation in case of IGBTs.

In case of a high inductive short circuit it is difficult for this conventional method to work well.

Another conventional detection method comprises the detection of a short circuit by comparing the gate charge at the gate with the gate source voltage between the gate and source ter minal of the gate-controlled power switch. The gate charge can for instance be acquired by sensing the gate current us ing a current mirror configuration or measuring a voltage drop across the gate resistance. Further, this conventional method requires calibration and is quite complex to imple ment. A further possible way for short circuit detection is to per form a direct current measurement of the flowing electrical current, however, this has an impact on the power loop and is also not easy to implement. Moreover, this way of short cir cuit detection is bulky and expensive to implement.

Accordingly, it is an object of the present invention to pro vide a method and apparatus which allow to detect a short circuit at a gate-controlled power switch fast and do not re quire a complex implementation.

This object is achieved according to a first aspect of the present invention by a fast short detection apparatus for de tection of a short circuit at a gate-controlled power switch comprising the features of claim 1.

The invention provides according to the first aspect a short circuit detection apparatus used for short circuit detection at a gate-controlled power switch, said apparatus comprising a measurement circuit adapted to generate a measurement sig nal in response to a voltage drop along a stray inductance of the gate-controlled power switch and a short circuit detection signal generation circuit adapted to generate a short circuit detection signal if the measure ment signal exceeds a reference voltage and the gate- controlled power switch is in a switched-on state.

In a possible embodiment of the short circuit detection appa ratus according to the second aspect of the present inven tion, the measurement circuit is connected to the gate- controlled power switch integrated in a package comprising a Kelvin source pin used to tap the voltage drop along the stray inductance of the gate-controlled power switch by the measurement circuit of the short circuit detection apparatus between the Kelvin source pin and the Source pin.

In a further possible embodiment, the short circuit detection apparatus according to the second aspect of the present in vention is adapted to detect a short circuit at a gate- controlled power switch comprising a MOSFET, in particular a SiC or GaN MOSFET.

In a still further possible embodiment of the short circuit detection apparatus according to the second aspect of the present invention, the comparator circuit is adapted to com pare a measurement signal generated by the measurement cir cuit with the self-generated reference voltage to generate a comparator output signal.

In a still further possible embodiment of the short circuit detection apparatus according to the second aspect of the present invention, the short circuit detection signal genera tion circuit comprises a voltage divider circuit adapted to measure an output volt age of a gate control signal output by a gate driver circuit and supplied to a gate terminal of the gate-controlled power switch to provide a measured gate voltage, a signal delay circuit adapted to delay the measured gate voltage with a delay time to provide a short circuit detec tion enable signal and a logic gate wherein the comparator output signal output by the comparator circuit is supplied via the logic gate as the short circuit detection signal to an input of the gate driver circuit, if the logic gate is enabled by the short circuit detection enable signal received from the signal delay cir cuit.

The invention provides according to the further aspect a fast short circuit detection method for detection of a short cir cuit at a gate-controlled power switch, the method comprising the steps of: providing a measurement signal in response to a voltage drop along a stray inductance of the gate-controlled power switch and generating a short circuit detection signal if the provided measurement signal exceeds a reference voltage, and the gate- controlled power switch is in a switched-on state.

The invention does not require a complex implementation, in particular there is no need for the provision of a complex analog or digital circuitry such as an FPGA. The method and apparatus according to the present invention provides for a very fast detection of a possible short circuit current. It can operate in different short circuit current conditions and is easy and inexpensive to implement. It is also not required to wait for a desaturation of the gate-controlled power switch. The method and apparatus according to the present in vention allows a normal operation of the gate-controlled pow er switch without disturbing or influencing its normal opera tion. The short circuit can be detected very fast within na noseconds. The voltage output by the gate driver can be used to activate the detection method according to the first as pect of the present invention. The method and apparatus ac cording to the present invention measures the voltage across a stray inductance of the gate-controlled power switch to de tect a short circuit current at the gate-controlled power switch. In a possible embodiment, the stray inductance of the gate- controlled power switch used for the short circuit detection comprises a stray inductance between a source terminal and a Kelvin Source pin of the gate-controlled power switch.

In a possible embodiment, the measurement signal is generated by a measurement circuit having a comparator circuit which compares the measurement signal with the reference voltage to generate a comparator output signal.

In a possible embodiment of the method according to the first aspect of the present invention, the generated short circuit detection signal is supplied to an input of a gate driver circuit to trigger an automatic switch-off of the gate- controlled power switch by the gate driver circuit within a switch-off period.

In a possible embodiment of the method according to the first aspect of the present invention, an output voltage of a gate control signal output by the gate driver circuit and applied to a gate terminal of the gate-controlled power switch via a gate resistor is measured by means of a voltage divider cir cuit to provide a measured output voltage of the gate driver circuit.

In a possible embodiment of the method according to the first aspect of the present invention, the measured output voltage of the gate driver circuit is delayed with a delay time by a signal delay circuit to provide a short circuit detection en able signal. In a still further possible embodiment of the method accord ing to the first aspect of the present invention, the compar ator output signal can be supplied via a logic gate as a short circuit detection signal to the input of the gate driv er circuit if the logic gate is enabled by the short circuit detection enable signal received from the signal delay cir cuit.

In a still further possible embodiment of the method accord ing to the first aspect of the present invention, the gate control signal applied by the gate driver circuit to the gate terminal of the gate-controlled power switch comprises a sig nal received from a microcontroller.

This signal can comprise a modulation signal, in particular a pulse width modulated signal, or one or more signal pulses.

In a still further possible embodiment of the method accord ing to the first aspect of the present invention, the refer ence voltage comprises an internal reference voltage derived from a steady-state voltage of the measurement signal.

In the following, possible embodiments of the different as pects of the present invention are described in more detail with reference to the enclosed figures.

Fig. 1 shows a block diagram to illustrate a possible exemplary embodiment of a short circuit detec tion apparatus according to an aspect of the present invention; Fig. 2 shows an abstract flowchart to illustrate a possible exemplary embodiment of a fast short circuit detection method according to a further aspect of the present invention;

Figs. 3A, 3B show different types of short circuits within a power electronic system to illustrate the oper ation of a fast short circuit detection method according to the present invention;

Fig. 4 shows a diagram to illustrate a possible embod iment of the method and apparatus according to the present invention;

Fig. 5 shows signal diagrams to illustrate the opera tion of a method and apparatus according to the present invention;

Fig. 6 shows further signal diagrams for illustrating the operation of a method and apparatus accord ing to the present invention;

Fig. 7 shows further signal diagrams for illustrating a possible exemplary embodiment of a method and apparatus according to the present invention;

Fig. 8 shows further signal diagrams to illustrate a possible exemplary embodiment of a method and apparatus in case of SC type 1 according to the present invention; Fig. 9 shows further signal diagrams to illustrate the operation of a method and apparatus in case of SC type 2 according to the present invention;

Fig. 10 shows a circuit diagram to illustrate a possi ble exemplary embodiment of an apparatus ac cording to the present invention;

Fig. 11 shows signal diagrams to illustrate a possible exemplary embodiment of a method and apparatus according to the present invention;

Figs. 12A,B,C show signal diagrams to illustrate experimental results for a short circuit scenario to illus trate the operation of a method and apparatus according to the present invention;

Figs. 13A,B show further signal diagrams to illustrate ex perimental results for another short circuit scenario to illustrate the operation of a meth od and apparatus according to the present in vention;

Fig. 14 shows signal diagrams to illustrate a double pulse test in a normal operation of a gate- controlled power switch.

As can be seen from the schematic block diagram of Fig. 1, a short circuit detection apparatus 1 according to an aspect of the present invention comprises in the illustrated exemplary embodiment a measurement circuit 2 and a short circuit detec tion signal generation circuit 3. The short circuit detection apparatus 1 as shown in the block diagram of Fig. 1 can be used for a short circuit detection at a gate-controlled power switch such as a MOSFET. The measurement circuit 2 of the ap paratus 1 is adapted to generate a measurement signal V _L s, _m in response to a voltage drop AV _LS along a stray inductance Ls of the respective gate-controlled power switch 4. The short cir cuit detection signal generation circuit 3 of the apparatus 1 is adapted to generate a short circuit detection signal Vsc if the measurement signal V _L s, _m does exceed a reference volt age V _ref and the gate-controlled power switch 4 is in a switched-on state. The measurement circuit 2 of the apparatus 1 can be connected to the gate-controlled power switch 4 in tegrated in a package comprising in a possible embodiment a Kelvin source pin S' used to tap the voltage drop AV _LS along the stray inductance Ls between the Kelvin Source pin and the Source pin of the gate-controlled power switch 4 by the meas urement circuit 2 of the short circuit detection apparatus 1. The gate-controlled power switch 4 tapped by the measurement circuit 2 can comprise a MOSFET, in particular a SiC MOSFET or a GaN MOSFET or a GaN HEMT. Further, the gate-controlled power switch 4 can also comprise for instance an IGBT.

Fig. 2 shows a flowchart to illustrate a possible exemplary embodiment of a fast short circuit detection method for de tection of a short circuit at a gate-controlled power switch according to a further aspect of the present invention. In the illustrated exemplary embodiment, the fast short circuit detection method comprises two main steps.

In a first step SI, a measurement signal V _L s, _m is provided in response to a voltage drop AV _LS along a stray inductance Ls of the gate-controlled power switch 4 such as a MOSFET. In a further step S2, a short circuit detection signal Vsc is generated automatically if the provided measurement signal VLS,m does exceed a reference voltage V _re f and the gate- controlled power switch 4 is in a switched-on state. In a possible embodiment, the stray inductance Ls providing the voltage drop comprises a stray inductance at a source termi nal S of the gate-controlled power switch 4. In a possible embodiment, the generated short circuit detection signal Vsc output by the short circuit detection signal generation cir cuit 3 can be supplied to an input of a gate driver circuit 5 as illustrated in Fig. 4 to trigger an automatic switch-off of the gate-controlled power switch 4 by the gate driver cir cuit 5 within a predefined switch-off period. Most gate driv ers comprise an SC detection input.

Figs. 3A, 3B show different examples of possible types of short circuits within a power electronic system.

The gate-controlled power switch 4 can comprise different kinds of materials. Different materials for power devices such as silicon carbide SiC or gallium nitride GaN provide for a gate-controlled power switch 4 having faster switching capabilities to reduce power losses and increase efficiency. However, during a short circuit situation, a current density of the electrical current flowing through the gate-controlled power switch 4 can be extremely high and may provoke a high increase of its junction temperature. This in turn results in a high stress of the gate-controlled power switch 4 and does limit its short circuit withstand capability. Since the gate- controlled power switch 4 has a reduced short circuit with stand capability, the reliability of the entire power elec tronic system is reduced. The fast short circuit detection method according to the present invention allows for a fast detection of a short circuit SC at the gate-controlled power switch 4 within a predefined reaction time of e.g. less than 300 nanoseconds. The implementation of the fast short circuit detection method according to the present invention requires only a simple circuitry thus improving the reliability of the power electronic system. With the implementation of the fast short circuit detection method according to the present in vention, it is possible to use sophisticated gate-controlled power switches such as silicon carbide SiC power switches or gallium nitride GaN power switches.

In a power electronic system, there are two common types of possible short circuits SC which may be defined as follows. A first short circuit type SCI comprises a hard switch fault HSF. In this scenario, the device is turned on with an al ready existing short circuit SC as also illustrated in Fig. 3A. The power device is driven by a driver circuit re ceiving for instance a PWM signal from a microcontroller. An other type of short circuit comprises a fault under load FUL. In this scenario, the short circuit SC does occur when the power device is in a conduction state as illustrated in Fig. 3A. In the illustrated scenario of Fig. 3B, two gate- controlled power switches 4 receive complementary PWM signals through driver circuits. If one of the two gate-controlled power switches 4 is in an on-state (conduction state) and there is a short circuit at the load of the other gate- controlled power switch 4, a fault under load FUL does occur.

The fast short circuit detection method according to the pre sent invention is adapted to detect a short circuit SC at the gate-controlled power switches 4 as illustrated for example in Figs. 3A, 3B using the voltage drop AV _LS along the stray inductance Ls of the gate-controlled power switch 4. In a possible embodiment, the voltage drop AV _LS can be measured between the source and driver source pin. In a possible em bodiment, the short circuit detection can be activated using the output voltage of the gate driver connected to the gate terminal of the gate-controlled power switch 4. In this em bodiment, the short circuit detection apparatus 1 according to the present invention is only active when the gate- controlled power switch 4 is in a switched-on state.

Fig. 4 shows a circuit diagram to illustrate a possible exem plary embodiment of a short circuit detection apparatus 1 ac cording to the present invention. In this embodiment, the short circuit detection apparatus 1 according to the present invention is used for a short circuit detection at a gate- controlled power switch 4. In the illustrated embodiment, the gate-controlled power switch 4 can be a MOSFET as shown in Fig. 4. The gate-controlled power switch 4 can also comprise other devices, in particular power switches such as IGBTs, GaN (HEMT) or SiCMOS, etc. integrated in different packages as discrete or integrated power modules. In the illustrated embodiment, the gate-controlled power switch 4 is integrated in a package having several connection pins. The gate- controlled power switch 4 comprises a gate G, a drain D and a source S. As illustrated in Fig. 4, the gate-controlled power switch 4 integrated in the package comprises an additional Kelvin source pin S' which allows to measure the voltage along the stray inductance Ls at the source S of the gate- controlled power switch 4. The voltage drop AV _LS along the stray inductance Ls of the gate-controlled power switch 4 is applied to the input of the measurement circuit 2 of the short circuit detection apparatus 1 as illustrated in Fig. 4. The measurement circuit 2 is adapted to generate the measure ment signal V _Ls,m in response to the received voltage drop AV _LS along the stray inductance Ls of the gate-controlled power switch 4. The short circuit detection signal generation cir cuit 3 connected to the measurement circuit 2 is adapted to generate a short circuit detection signal Vsc if the measure ment signal V _L s, _m received from the measurement circuit 2 does exceed a reference voltage V _ref and if the gate-controlled power switch 4 is in a switched-on state. The measurement circuit 2 is connected to the gate-controlled power switch 4 integrated in the package comprising the Kelvin source pin S' which is used to tap the voltage drop AV _LS along the stray inductance Ls of the gate-controlled power switch 4 by the measurement circuit 2.

In the embodiment shown in Fig. 4, the short circuit detec tion signal generation circuit 3 comprises two main compo nents, i.e. a comparator circuit 3A and an enabling SC detec tion circuit 3B. The measurement signal V _L s, _m generated by the measurement circuit 2 is compared by the comparator circuit 3A of the short circuit detection signal generation circuit 3 with the reference voltage V _ref to generate a comparator out put signal VLS, _C as shown in Fig. 4. This comparator output signal VLS, _C is applied to the enabling SC detection circuit 3B as shown in Fig. 4.

A possible implementation of the enabling SC detection cir cuit 3B is shown in the circuit diagram of Fig. 10. In the illustrated embodiment of Fig. 10, the SC detection signal generation circuit 3 comprises an enabling SC detection cir cuit 3B having a voltage divider circuit 31, a signal delay circuit 32 and a logic gate 33. As illustrated in the circuit diagram of Fig. 10, the enabling SC detection circuit 3B can comprise a voltage divider circuit 31 having to resistors R9,R10 which is adapted to measure an output voltage of a gate control signal VG output by a gate driver circuit 5 and supplied to a gate terminal G of the gate-controlled power switch 4 through a gate resistor to provide a measured gate voltage V _G , _m . Further, the enabling SC detection circuit 3B can comprise a signal delay circuit 32 which is adapted to delay the measured gate voltage V _G , _m with a predefined delay time t _del to provide a short circuit detection enable signal Vsc, _en as shown in the circuit diagram of Fig. 10. Further, the enabling SC detection circuit 3B can comprise a logic gate 33 . The comparator output signal VLS, _C output by the com parator circuit 3A can be supplied via this logic gate 33 as the short circuit detection signal Vsc to an input SC of a gate driver circuit 5 if the logic gate 33 is enabled by the short circuit detection enable signal Vsc, _en received from the comparator of the signal delay circuit 32 .

Fig. 4 shows the short circuit detection signal Vsc supplied to the input SC of the gate driver circuit 5. The generated short circuit detection signal Vsc generated by the short circuit detection signal generation circuit 3 is supplied to the input SC of the gate driver circuit 5 to trigger an auto matic switch-off of the gate-controlled power switch 4 by the gate driver circuit 5 within a predefined switch-off period. The gate control signal Vs output by the gate driver circuit 5 is applied to the gate terminal G of the gate-controlled power switch 4 as illustrated in Fig.4 . In a possible embod iment, the gate control signal Vs output by the gate driver circuit 5 can be applied via a resistor Rc _ext to the gate ter minal G of the gate-controlled power switch 4.

In a possible embodiment, the gate control signal Vs output by the gate driver circuit 5 can be measured by means of the voltage divider circuit 31 of the enabling SC detection cir- cuit 3B as illustrated in the circuit diagram of Fig. 10. This measured gate voltage V _G is delayed by the delay circuit 32 of the enabling SC detection circuit 3B with a delay time t _d e _l to provide a short circuit detection enable signal Vsc, en by means of a comparator as shown in Fig. 10. The comparator output signal VLS, _C output by the comparator circuit 3A can be supplied via the logic gate 33 as the short circuit detection signal Vsc to the input SC of the gate driver circuit 5 if the logic gate 33 is enabled by the short circuit detection enable signal Vsc, en received from the signal delay circuit 32. In a possible implementation, the logic gate 33 can com prise an AND gate which receives as a first input the compar ator output signal VLS, _C output by the comparator circuit 3A and as a second input signal the short circuit detection ena ble signal Vsc, en output by the comparator of the signal delay circuit 32 provided within the enabling SC detection circuit 3B. The output of the AND gate 33 can be connected to the SC input of the gate driver circuit 5 to carry the short circuit detection signal Vsc -

In a possible embodiment, the gate control signal V _G applied by the gate driver circuit 5 to the gate terminal G of the gate-controlled power switch 4 can comprise any modulating pulse or signal, in particular a pulse width modulated, PWM, signal, received from a signal source, in particular from a microcontroller as also shown in Fig. 4. The gate driver cir cuit 5 can generate a fault indication signal FLT when an au tomatic switch-off of the gate-controlled power switch 4 has been performed by the gate driver circuit 5. In the illus trated embodiment of Fig. 4, the reference voltage V _ref sup plied to the comparator circuit 3A can comprise an internal reference voltage which may be derived from a steady-state voltage of the measurement signal V _L s, _m . In an alternative em- bodiment, the reference voltage V _ref can also be generated by a separate reference voltage source.

The gate-controlled power switch 4 can comprise a driver source pin such as the power source pin S as shown in Fig. 4. The stray inductance Ls between the two pins is a result of the mechanical interconnection and can be in the range of several nanoHenrys. During switching transients of the gate- controlled power switch 4, i.e. turn-on and turn-off of the gate-controlled power switch 4, the electrical current I _D flowing through the gate-controlled power switch 4 does change rapidly in a range of nanoseconds and has as a result a voltage drop AV _LS along the stray inductance Ls between the pins S, S'as follows:

Vis = Ls x dID/dt

By measuring the measurement signal V _LS,m one gets the infor mation whether the drain current ID has changed rapidly from a normal operation condition or not and also about its dura tion. With a slow variation of the electrical current the measurement signal V _Ls,m is close to 0 V. Fig. 5 shows an ex ample of waveforms during a turn-on transient of the gate- controlled power switch 4. Between the time to and ti, the electrical current ID does increase from zero to its nominal value (dl/dt>>0) which lasts normally in a range of several nanoseconds. The measurement signal V _Ls,m increases according to the above given equation. During time ti and t.2, the elec trical current ID decreases (dl/dt<<0) and the measurement signal V _Ls,m does change its polarity from positive to nega tive. In a normal operation condition of the gate-controlled power switch 4, the switching time period (ti-to) is limited and known. In the on-state of the gate-controlled power switch 4 (t>12), the electrical current I _D does increase slowly depending upon its load and dID/dt is close to zero resulting in a measurement signal V _L s, _m being approximately close to 0 V as illustrated in Fig. 5.

In case of a short circuit scenario as illustrated in Fig. 3A, the switching time (ti-to) of the electrical current I _D does drastically increase and it is reflected in the dura tion of the voltage drop VLS. During the turn-on transient, a long duration of V _L s, _m (i.e. longer than normal) can be used as an indicator of the first switching scenario, i.e. the short circuit type SCI being a hard switch fault HSF as shown schematically in Fig. 3A. In case of another short circuit scenario SC2 as shown in Fig. 3B, i.e. fault under load FUL, the electrical current I _D does rapidly increase (dl/dt>>0) when the device has already passed the switching time (t>t2) and therefore the measurement signal V _L s, _m does increase, too. Any increment of V _L s, _m for the time t>t2 can be used as an in dicator of such a failure. In a possible embodiment, the du ration of V _LS , _m can be used to detect either a short circuit type SCI or a short circuit type SC2 as illustrated in Figs. 3A, 3B.

In a possible embodiment, the measurement signal V _L s, _m can be measured and adapted using a simple circuitry as implemented in the block 2 shown in the circuit diagram of Fig. 4. The measurement signal V _L s, _m output by the measurement circuit 2 can be compared with a reference voltage VLS,re _f as shown in Fig. 4. The value of the reference voltage VLS,re _f can be slightly higher than the steady-state value of the measure ment signal V _L s, _m . The output signal of the comparator 3A, i.e. the comparator output signal VLS, _C , can be a square shaped signal having a duration which is proportional to the duration of the measurement signal V _L s, _m and consequently pro portional to the duration of the electrical current ID as al so illustrated schematically in the signal diagrams of Fig. 6. In this embodiment, the comparator output signal VLS, _C can be used as an indicator of a short circuit SC. An example of this procedure during a turn-on transient is illustrated in the signal diagrams of Fig. 6.

In a preferred embodiment, the short circuit detection method is activated just during a switch-on state of the observed gate-controlled power switch 4. Accordingly, the short cir cuit detection signal Vsc is only generated if the provided measurement signal V _L s, _m does exceed a reference voltage Vis, _ref and if the gate-controlled power switch 4 is at the same time in a switched-on state. Accordingly, in a possible embodiment, the short circuit detection method according to the present invention is activated just during the on-state period of the gate-controlled power switch 4. In a possible embodiment, the method is enabled by using an output signal of the gate driver circuit 5, i.e. the gate driver signal V _G as shown in Fig. 4. This voltage V _G can be measured and an enable signal Vsc,en can be set high from nanoseconds after a positive edge of the gate control signal V _G output by the gate driver circuit 5 to avoid a false positive detection during the turn-on transient. In a possible embodiment, the delay time t _d ei between the positive edge of the gate control signal V _G and the enable signal can be adjustable and can de pend on a switching time of the gate-controlled power switch 4 during normal operation. Consequently, the short circuit detection provided by the method according to the present in vention is enabled in a preferred embodiment after the time required for a normal switching transient of the gate- controlled power switch 4. Fig. 7 shows waveforms of a procedure for enabling the short circuit detection during a turn-on transient of the gate- controlled power switch 4. In the illustrated example, the gate-controlled power switch 4 is turned on with the gate control signal V _G on-voltage VG _on and turned off with the gate control off-voltage VG _0ff . The delay time t _d ei is defined as the time period between time to and time t4 as illustrated in Fig. 7. Accordingly, in the illustrated example, after time t=t4, the short circuit detection method according to the present invention is enabled.

Fig. 8 shows exemplary waveforms for a short circuit detec tion method according to the present invention in a short circuit scenario of the first type SCI when compared to a normal operation nOP(dotted line). In the illustrated exam ple, the gate-controlled power switch 4 is turned on at time t=to and the output signal from the gate driver circuit 5 steps up from VGo _ff to VG _on , i.e. from the off-voltage to the on-voltage of the gate control signal. At the same time, the electrical current ID flowing through the gate-controlled power switch 4 starts rising as well as the measurement sig nal VLS,m. If the measurement signal V _L s,m is higher than the reference voltage V _L s,re _f the comparator output signal VLS, _C is set high too (at t=ti). At time t=t2, the delay time t _d ei has passed and the short circuit detection mechanism according to the present invention is activated setting the enable signal Vsc, en to a high level. Due to the short circuit SC at the time t>12, the electrical current ID is still rising and therefore the signal VLS, _C is still high in contrast to the no failure case. Both the signals VLS, _C , i.e. the comparator out put signal, and the short circuit detection enable signal Vsc, en are both at a high level which is an indicator of an occurred short circuit SC. As a result, the failure signal, i.e. the short circuit detection signal Vsc is set high, too, indicating the detection of the occurred short circuit SC. In a possible embodiment, the signal Vsc can be latched for a determined and adjustable time.

Fig. 9 shows exemplary waveforms for a short circuit detec tion of a short circuit of the second type SC2 when compared to a normal operation nOP(dotted line). In case that a short circuit of the second type II (SC2) does occur, the fast short circuit detection method according to the present in vention does operate in a similar way as in case of a short circuit of the first type SCI. An example of a short circuit scenario of the second type SC2 is presented in Fig. 9 where the electrical current ID during a normal operation is de picted in dotted line. In this case, the delay time t _dei is not there and the enable signal is already high. Accordingly, any pulse from the signal Vsc, _c can trigger the detection and set the failure signal, i.e. the short circuit detection sig nal Vsc, to a high value. Accordingly, the detection of a short circuit in the second scenario SC2 is faster than the detection of a short circuit in the first short circuit sce nario SCI due to the absence of the enabling delay time t _dei .

Fig. 10 shows a possible exemplary implementation of a short circuit detection apparatus 1 according to the present inven tion. The short circuit detection apparatus 1 is used for short circuit detection at the gate-controlled power switch 4 as shown in Fig. 10. The short circuit detection apparatus 1 comprises a measurement circuit 2 and a short circuit detec tion signal generation circuit 3. In a possible embodiment, the voltage drop AV _LS across the stray inductance Ls of the gate-controlled power switch 4 is measured using a compen- sated voltage divider composed by resistors Rl, R2 and capac itors Cl, C2 as illustrated in Fig. 10.

With the compensate voltage divider of the measurement cir cuit 2 the resistance and the capacitance of the capacitors Cl, C2 can be given by:

Rl x Cl = R2 x C2

In a possible implementation, the voltage divider of the measurement circuit 2 can be designed to have a voltage V _LS , _I in a range of -2.5 to 2.5 V. A bias voltage V _ias can be added to this voltage V _LS , _I to create an offset thus avoiding the use of any negative power supply in the circuitry. The re sulting voltage can be amplified by a factor 2 using a high frequency operational amplifier as shown in the circuit dia gram of Fig. 10. The output of the operational amplifier forms the measurement signal V _L s, _m which can be in a range from 0 to 5 V with a steady-state voltage at 2.5 V. During the turn-on transient of the gate-controlled power switch 4, a high positive change of the electrical current dl/dt pro duces a voltage drop of V _L s, _m in a range of 0 to 2.5 V because in the illustrated embodiment the pin S' forms the ground of the illustrated circuit. The measurement signal V _L s, _m can be compared in the illustrated embodiment of Fig. 10 with a self-generated reference voltage V _ref by means of the compara tor circuit 3A as shown in Fig. 10. In the illustrated embod iment of Fig. 10, the reference voltage V _ref comprises an in ternal reference voltage which is derived from a steady-state voltage of the measurement signal V _L s, _m . In a possible imple mentation, the reference voltage V _L s, _ref can be around 90% of the steady-state voltage of the measurement signal V _L s, _m . In this case, the reference voltage V _L s, _ref can be around 2.25 V and is stable due to capacitor C3 illustrated in Fig. 10. Ac cordingly, in the illustrated embodiment, the measurement circuit 2 is also adapted to generate an internal reference voltage derived from a steady-state voltage of the measure ment signal V _L s, _m and supplied to the comparator circuit 3A of the short circuit detection signal generation circuit 3. In this kind of simple self-generated and stable reference volt age V _ref , any influence of the tolerance and temperature of the components such as the stray inductance Ls or passive components and integrated circuits can be controlled. In case that a positive and a high current increase or change dl/dt does occur, the measurement signal V _L s, _m does fall below the derived reference voltage V _ref and the comparator circuit 3A generates a comparator output signal VLS, _C at a high signal level.

In a preferred embodiment, the short circuit SC detection is only activated during an on-state of the gate-controlled pow er switch 4. The output voltage of the gate driver circuit 5 can be measured and adjusted using a simple voltage divider circuit 31 having resistors R9,R10 within the enabling SC de tection circuit 3B of the short circuit detection signal gen eration circuit 3. The resulting signal V _G , _m can be in a range of 0 V to 5 V . In the illustrated implementation of Fig. 10, the signal delay circuit 32 comprises a low-pass filter LPF which can be composed by a resistor R _d ei and a capacitor C _d ei used to provide a delay time t _d ei . The filtered output signal of the low-pass filter V _G ,I can be compared by a comparator of the signal delay circuit 32 with a reference voltage V _ref , _d ei as shown in the circuit of Fig. 10 to generate the short cir cuit detection enable signal Vsc, en supplied to the logic gate 33 of the short circuit detection signal generation circuit 3B forming part of the short circuit detection signal genera- tion circuit 3. Once the short circuit detection enable sig nal Vsc,en is set high, the failure signal, i.e. the short circuit detection signal Vsc, can be triggered by the compar ator output signal VLS,C output by the comparator circuit 3A to detect a short circuit having occurred at the gate- controlled power switch 4.

Fig. 11 shows exemplary waveforms to illustrate the operation of the enabling SC detection circuit 3B. In the illustrated embodiment, the logic gate 33 is formed by an AND logic gate. The components utilized in this embodiment can be suitable for a high frequency with extremely low propagation delay times in the range of less than 10 nanoseconds.

Figs. 12 A,B,C illustrate experimental results of a short circuit scenario of the first type SCI. Fig. 12A shows a drain current ID, Fig. 12B illustrates the drain source volt age VDS and Fig. 12C illustrates the gate voltage VGS. A con ventional method may detect a short circuit SC after 950 na noseconds and a total withstand time tsc,desat may be around 1.15 microseconds. In contrast, the fast short circuit detec tion method FSCP according to the present invention can de tect a short circuit SC around 200 nanoseconds after it has occurred by starting a soft turn-off procedure. The total withstand time tsc,Fscp is around only 300 nanoseconds, i.e. about four times faster than the conventional detection meth od.

The experimental results for the other short circuit detec tion scenario SC2 are illustrated in the signal diagrams of Figs. 13 A,B . Fig. 13A shows at the top the drain current with a drain source voltage at the gate-controlled power switch 4 and on the bottom the gate source voltage. With the fast short circuit detection method according to the present invention as illustrated in Fig. 13A, a detection time of around 54 nanoseconds can be achieved where the total short circuit withstand time tsc,Fscp is around only 150 nanoseconds. In contrast, with a conventional detection method as illus trated in Fig. 13B, it can be detected only after 450 nano seconds with a total time of around 750 nanoseconds. Conse quently, the fast short circuit detection method according to the present invention is in the second short circuit scenario SC2 around five times faster than the conventional method.

The fast short circuit detection method according to the pre sent invention does not interfere with the normal switching transient of the gate-controlled power switch 4. To test this, a standard double pulse test has been performed with an SiC MOSFET device 4 of 80 milliohm and 1200 V. A maximum peak current for the gate-controlled power switch 4 is 60A (taken from a datasheet). The experimental results are shown in the signal diagrams of Fig. 14. The top part of Fig. 14 shows the drain source voltage. The bottom part of Fig. 14 shows the gate voltages. The DC link voltage is 600 V and the drain current is more than 60 amps and no false positives are fea sible. This does confirm the compatibility of the fast short circuit detection method according to the present invention with a normal operation of the gate-controlled power switch 4.