[0001] The present invention relates to a method for generating oscillator signals and apparatus comprising a synthesizer.

BACKGROUND

[0002] This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.

[0003] In some apparatuses which are able to transmit and receive signals in multiple bands or otherwise operate in large radio frequency spectrum, - local oscillator signals on a large frequency range may be generated. This may be achieved by using a reference clock signal having a substantially constant frequency and multiplying that frequency by an appropriate phase selection control to achieve the desired local oscillator frequency. In such systems the so called digital period synthesis (DPS), also called as flying-adder frequency synthesizer, may be used to form the local oscillator signals. However, possibilities to use the digital period synthesis may be limited due to maximum operation frequency and deterministic jitter due to the digital period synthesis operation principle.

SUMMARY

[0004] Various embodiments provide a method and apparatus for generating oscillator signals in which the frequency of the oscillator signals may be adjusted. In some embodiments the digital period synthesis and a least significant bit (LSB) modulation technique are utilized. The digital period synthesis is inherently a direct high precision frequency synthesis method.

[0005] Various aspects of examples of the invention are provided in the detailed description. [0006] According to a first aspect, there is provided a method comprising:

receiving a reference clock signal;

obtaining a set of phase shifted reference clock signals;

obtaining a phase selection control;

using a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

using a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0007] According to a second aspect, there is provided an apparatus comprising:

an input for receiving a reference clock signal;

a reference generator for obtaining a set of phase shifted reference clock signals; a phase accumulator for obtaining a phase selection control;

a phase selector adapted to use a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

a variable delay buffer adapted to use a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0008] According to a third aspect, there is provided an apparatus comprising at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

receive a reference clock signal;

obtain a set of phase shifted reference clock signals;

obtain a phase selection control;

use a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

use a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0009] According to a fourth aspect, there is provided a computer program product including one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:

receive a reference clock signal; obtain a set of phase shifted reference clock signals;

obtain a phase selection control;

use a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

use a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0010] According to a fifth aspect, there is provided an apparatus comprising:

means for receiving a reference clock signal;

means for obtaining a set of phase shifted reference clock signals;

means for obtaining a phase selection control;

means for using a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

means for using a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0011] In some embodiments the delaying comprises:

delaying in a first delay path a rising edge of the selected phase shifted reference clock signal to obtain a rising edge of an output clock signal; and

delaying in a second delay path a falling edge of the selected phase shifted reference clock signal to obtain a falling edge of the output clock signal.

[0012] In some embodiments an inverted selected phase shifted reference clock signal is obtained; and the inverted selected phase shifted reference clock signal is used in the second delay path.

[0013] In some embodiments the output clock signal is used as at least one of the following:

a local oscillator signal for an RF mixer; a clock signal for an analog-to-digital converter; a clock signal for a digital-to-analog converter; a clock signal for synchronous digital logic.

[0014] In some embodimentsadding the phase selection control is added to a previous accumulated value when the selected phase shifted reference clock signal changes from a first state to a second state, wherein the accumulated value after the addition forms the phase selection control to be used in the selection of the next phase shifted reference clock signal. [0015] The digital period synthesizer may enable power- and area-efficient clock and local oscillator signal generation especially in complex system-on-chip architectures. There is also provided an implementation solution to the LSB modulation technique. In some embodiments the LSB controlled delay is synchronized to the corresponding DPS output pulse. Additionally, there is also provided a transistor level implementation for a variable delay buffer. These implementations may be used to reduce the deterministic jitter of the DPS architecture. The enhanced jitter performance may respectively enable the utilization of the digital period synthesizer in high performance applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a more complete understanding of example embodiments of the present invention, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:

[0017] Figure la illustrates some signal waveforms in connection with an LSB- modulator when a variable delay is added ;

[0018] Figure lb illustrates some signal waveforms in connection with an LSB- modulator when a variable delay is added the operation principle and the effect of the LSB-modulation technique to deterministic jitter and phase noise;

[0019] Figure lc illustrates some signal waveforms in connection with an LSB- modulator when a variable delay is added the operation principle and the effect of the LSB-modulation technique to deterministic jitter and phase noise;

[0020] Figure 2a shows an exemplary signaling of a DPS-modulator without synchronization;

[0021] Figure 2b shows an exemplary signaling of a DPS-modulator with synchronization;

[0022] Figure 3a shows an example of a frequency synthesizer;

[0023] Figure 3b shows an example of a phase accumulator;

[0024] Figure 4 shows a simplified block diagram of an apparatus according to an example embodiment;

[0025] Figure 5 depicts exemplary signaling diagrams of the operation of the frequency synthesizer according to an example embodiment; [0026] Figure 6 depicts another exemplary signaling diagrams of the operation of the frequency synthesizer according to an example embodiment;

[0027] Figures 7a, 7b and 7c depict an example implementation of the variable delay buffer 324 at different levels

[0028] Figure 8 depicts a method according to an embodiment;

[0029] Figure 9 depicts some simulation results;

[0030] Figure 10 shows a block diagram of an apparatus according to an example embodiment;

[0031] Figure 11 shows an apparatus according to an example embodiment;

[0032] Figure 12 shows an example of an arrangement for wireless

communication comprising a plurality of apparatuses, networks and network elements.

DETAILED DESCRIPTON OF SOME EXAMPLE EMBODIMENTS

[0033] The following embodiments are exemplary. Although the specification may refer to "an", "one", or "some" embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment. Single features of different embodiments may also be combined to provide other embodiments.

[0034] In the following an example system is described in which the digital period synthesis may be used to form local oscillator signals.

[0035] One source of deterministic jitter in the digital period synthesis arises from its operation principle: generation of output signal from discrete number of reference phases. When the clock signal generated by the digital period synthesis is provided to an analog-to- digital converter (ADC) and/or to a digital-to-analog converter (DAC) the deterministic jitter may cause deterioration of the signal-to-noise ratio (SNR). Correspondingly, when used as a local oscillator signal the deterministic jitter may cause spurious tones or rise in the phase noise floor, which also may reduce the SNR considerably. In some embodiments of a method the deterministic jitter of the DPS architecture may be reduced and therefore the digital period synthesizer may also be utilized in higher performance applications. The deterministic jitter due DPS operation is directly proportional to the delay between the reference phases, hereafter referred as the unit delay. One solution to reduce the deterministic jitter is to reduce the unit delay. However, this could lead to considerable increase in the number of reference phases. Consequently, the power and area dissipation of the reference phase generation might become excessive.

[0036] An idea of the LSB-modulation is based on utilization of variable delay, which may be controlled by least significant bits (LSB) of an accumulator output sum. The variable delay is used to provide a linear digital-to-delay conversion, which covers a delay range of one unit delay, with substantially equally sized steps. For convenience, Figures la— lc show the operation principle of the LSB-modulator with 2 LSB bits. This example highlights the reduction of the deterministic jitter and phase noise that may be achieved by using this technique. It should be noticed that this jitter reduction method may not impair the other performance characteristics of the digital period synthesis, such as frequency tuning resolution and switching speed. Additionally, the LSB-modulator implementation may be power efficient and area efficient. Figure la depicts some signal waveforms in connection with an LSB-modulator when a variable delay is added. The deterministic jitter compared to ideal signal is marked as grey. The waveform at the top of Figure la depicts an ideal signal. The waveform elk below the ideal signal depicts an example of the output signal of the digital period synthesis. Next, some delay values ΔΤ of the LSB-modulator controlled by the accumulator control (CLSB) and corresponding LSB-modulated output signal out are shown. Figure lb illustrates the effect of the LSB-modulation to the deterministic jitter histogram and Figure lc illustrates the effect of the LSB-modulation to the output spectrum.

[0037] Figure 3 a depicts an example of a frequency synthesizer 300 which may utilize the so-called LSB-modulator 320. An idea of the digital period synthesis architecture may be to synthesize instantaneous output periods, whose length may be digitally controlled. In this embodiment the frequency synthesizer 300 may comprise a digital period synthesizer 302 and the LSB-modulator 320. The digital period synthesizer 302 may comprise a reference generator 304 for generating multiple output signals having the same frequency than the reference signal 301 but different phases. The multiple outputs of the reference generator 304 may be coupled to a phase selector 306 which may select one of the outputs of the reference generator 304 on the basis of phase selection control signals 308 (CMSB). The phase selection control signals 308 may be generated by a phase accumulator 310 by using a digital word frequency control input 312 (few) and an output signal 314 (elk) from the phase selector 306 as will be described later in this specification.

[0038] In this embodiment the LSB-modulator 320 comprises an input buffer 322, a variable delay buffer 324 and a control synchronizer 326. The LSB-modulator 320 may utilize two delay paths 328, 330 in the generation of one or more output signals 332 (out), 334 (outx). The first delay path 328 may utilize rising edges of the signal 314 from the digital period synthesizer 302. Correspondingly, the second delay path 330 may utilize the falling edges of the signal 314 from the digital period synthesizer 302.

[0039] The synchronization may improve the operation of the LSB-modulator for at least two reasons. First, both rising and falling edges of the output signal may experience the same delay. If not, the output pulse width may be modulated, which may cause increase in the jitter as well as phase noise and spurious tone levels. Second, the DPS architecture may be able to produce output frequencies in very wide range. Therefore, the timing window in which the pulse have to be delayed may vary a lot. Figure 2a depicts an exemplary signaling of a DPS-modulator without synchronization. In this case, the output signal violates the corresponding timing window resulting the above mentioned unwanted pulse-width modulation, which is marked as gray. Figure 2b shows the same situation with an example synchronization method. Consequently, the timing window is moved around the corresponding output pulse which may remove the violation and improve the operation of the LSB-modulator.

[0040] In the following the operation of the frequency synthesizer 300 will be described in more detail. The reference generator 304 may receive a reference signal 301 from an oscillator 450 (Figure 4), such as a crystal oscillator. The frequency of the reference signal 301 may be different in different embodiments and may depend on the frequency range in which the frequency synthesizer 300 should be able to operate. For example, the frequency of the reference signal 301 may be several tenths or hundreds of MHz. The reference generator 304 may generate multiple output signals Pi, P ₂ , . . . , PN having the same frequency than the reference signal 301 but different phases as can be seen from Figure 5. In other words, the reference generator 304 forms a set of N reference phases from a single reference signal cycle with substantially equal time difference to each other, TUD, SO that TREF=N-TUD. [0041] The phase accumulator 310 receives a frequency control input 312 which may comprise a certain number N of bits (e.g. a 32-bit control word fcw[0:31]). The frequency control input 312 may define the multiplication ratio of the digital period synthesizer 302 i.e. the ratio between the frequency of the output of the digital period synthesizer 302 and the frequency of the reference signal. The multiplication ratio need not be an integer number but may also comprise a fractional part, such as 4.25, 9.125, 120.1872006232417 etc.

[0042] In some embodiments the phase accumulator 310 comprises a digital N-bit adder 310a and an N-bit register 310b (Figure 3b) whose output (s[0:N-l]) may be fed back to an adder input. The M+N _L S _B most significant bits (MSB) of the sum (S[N-(M+N _L S _B ) :N- 1 ]) may form the digital control which may be used for the phase selection and LSB- modulation. The MSB part of this sum may be provided to a one-hot decoder which may produce a phase selection signal 308 to the phase selector 306. Correspondingly, the LSB part of this sum may produce a LSB-modulation control 316 for the LSB-modulator 300. The output 314 from the phase selector may be used as a timing signal for the phase accumulator 310. When there is a certain change of state of the output 314 of the phase selector (e.g. a rising edge when the state may change from the logical 0 state to the logical 1 state), the accumulator control signals 310 and 316 are refreshed. The phase selection control 310 may produce a phase selection signal to the phase selector 306 when there is a certain change of the state of the output of the digital period synthesizer 302 (e.g. a rising edge). The selected phase is coupled to the output of the digital period synthesizer 302.

[0043] Both the register 310b and the one-hot decoder 310c may use the output of the digital period synthesizer 302 as the timing signal.

[0044] The term one-hot decoder means that only one of the plurality of output signals may be at the logical 1 state at the same time. Hence, only one phase may be selected at one time by the phase selector 306.

[0045] The phase selector 306 may select one of these reference phases at a time according to the phase selection control, selo...selM-ι· The selected phase is propagated to the output to form the synthesized signal. The phase accumulator 310 may be clocked with the output clock to generate a new selection control from the N-bit frequency control input 312. The actual phase selection control is formed in the one-hot decoder, where the m most significant bits of the accumulator output s[0:N-l] are used to generate 2 ^m -bit phase selection control.

[0046] Figure 5 is provided to further illustrate the operation of the digital period synthesizer 302. This Figure shows some exemplary waveforms with eight reference phases and 5-bit (=n) phase accumulator when fcw[4:0]=10101 that is in decimal notation 21. Hereafter, the decimal notation of the frequency control word is marked as capital letters, i.e. FCW=21. The exemplary operation of the DPS architecture is as follows. First, at time instant t=0, the phase accumulator has an initial state of 0, i.e SMSB[4:0]=[00000]. This may correspond to one-hot decoded phase selection signals values of CMSB,I=1 and CMSB,2 - · · CMSB,8~0. AS a result, the first rising edge of the synthesized output signal, out, may be constituted from the reference phase Po. This phase propagates through the phase selector to the output and triggers the phase accumulator to increment the phase selection control by FCW=21. After a time delay of T _D ,ACC from the rising edge of phase Po, the accumulation sum is ready and the accumulator output is SMSB [4:0]=[10101] of which the three (=m) most significant bits are used for phase selection. Correspondingly, this sum is one-hot decoded to select reference phase P ₅ that forms the following rising edge of the output signal. The accumulator may be trigged again to calculate the next selection control by incrementing the phase selection control by FCW=21. As a result, the corresponding rising edge is constituted from reference phase P ₂ . Correspondingly, the phase Φ ₇ form the next rising edge. At the fifth accumulation the value is SMSB [4:0]=[10100] resulting the rising edge to be generated from P ₅ . Consequently, instantaneous output period is 6-TUD instead of the preceding 5-TUD. This fluctuation of the period will result an average output period to be a fractional multiplication of the unit delay, in this case 5.25-TUD. Figure 5 shows also the ideal output signal, clkideai, with period of 5.25-TUD. The DPS architecture may quantize the output period information of the ideal signal with finite resolution of TUD.

[0047] In the following the operation of the LSB-modulator 320 according to an example embodiment will be described in more detail. The input buffer 322 receives the output signal 314 from the phase selector 306. The output signal 314 is buffered by a first buffer 322a and provided to a first variable delay buffer 324a. The input buffer 322 also forms an inverted output signal 314a (clkx) from the output signal 314 by an inverter 322b, buffers the inverted output signal 314a in a second buffer 322c, and provides the buffered inverted output signal 314a to a second variable delay buffer 324b.

[0048] The output signal 314 and the inverted output signal 314a may be also provided to the control synthesizer 326. In this embodiment the control synthesizer 326 may comprise a first register 326a and a second register 326b. The first register 326a receives the LSB part (CLSB) of the contents of the phase accumulator 310. This part may also be called as an LSB-delay control. Also the second register 326b receives the LSB part (CLSB) of the contents of the phase accumulator 310. The first register 326a uses the output signal 314 as a clock signal to copy the value at the input of the first register 326a to the output of the first register 326a at the moment determined by the clock signal (i.e. the output signal 314). Correspondingly, the second register 326b uses the inverted output signal 314a as a clock signal to copy the value at the input of the second register 326b to the output of the second register 326b at the moment determined by the inverted clock signal (i.e. the inverted output signal 314a). In other words, the registers 326a, 326b synchronize the control signal, which is to be provided to the variable delay buffer, with the output of the phase selector 306.

[0049] In order to achieve high operation frequency, the rising and falling edges of the output signal 314 may be delayed at separate paths in the variable delay buffer 324. The buffered output signal 314 may be delayed by the first variable delay buffer 324a and the buffered inverted output signal 314a may be delayed by the second variable delay buffer 324b. The delay value of the first variable delay buffer 324a may be adjusted by providing the output of the first register 326a to the delay control input 324c of the first variable delay buffer 324a. Correspondingly, the delay value of the second variable delay buffer 324b may be adjusted by providing the output of the second register 326b to the delay control input 324d of the second variable delay buffer 324b.

[0050] The LSB-modulator 320 further comprises a latch circuit 336. The latch circuit 336 operates e.g. as a set-reset latch (SR-latch). Hence, a state transition from a first state to a second state in the set input 336a toggles the state of the output 332 (out) and the inverted output 334 (outx). Respectively, a state transition from the first state to the second state in the reset input 324g toggles the state of the output 332 (out) and the inverted output 334 (outx). When there is a state transition from the second state to the first state in the set input 336a or a state transition from the second state to the first state in the reset input 336b, the state of the output 332 and the inverted output 334 is not affected. In the example embodiments it is assumed that the first state is the logical 0 state and the second state is the logical 1 state. Hence, a rising edge at the set input sets the output 332 (when the reset input is in the first state) and a rising edge at the reset input resets the output 332 (when the set input is in the first state). In some other embodiments the first state may be the logical 1 state and the second state may be the logical 0 state.

[0051] Figure 6 depicts the signaling of the LSB-modulator 320 according to an example embodiment. It can be seen that the window for pulse delaying is quite small, wherein at high frequencies the falling edges of both signals (clk _L sB, CUCXL _S B) may be distorted. These parts of the signals are marked as grey in Figure 6. The SR-latch at the output of the LSB-modulator may utilize only the rising edges of the separate paths, and therefore produces an output signal (out, outx) without the distortion or at least with less distortion. The SR-latch provides also differential output signaling. Utilizing the separate paths, the maximum operation frequency of the variable delay buffer may be increased.

[0052] The specific transistor level implementation of the LSB-modulator may have some challenges to address. First, the variable delay buffer should be able to provide accurate enough and linear digital-to-delay conversion with constant step size over possible variations in operating voltages, temperature, and components of the apparatus (process level). Second, at high operation frequency the delaying of the output signal may have to be realized in very narrow timing window.

[0053] The synchronization of the delay control may be one element in order to achieve a dynamic and accurate enough digitally controlled delay buffer. Especially at high operation frequencies, the window, in which the pulse delay has to be realized, may be very narrow.

[0054] Figure 6 depicts an example implementation for the synchronization. In order to achieve high operation frequency, the rising and falling edges of the input signal are delayed at the separate paths. Figure 6b depicts an example of the signaling of the example implementation. It can be seen that the window for pulse delaying is so small at high frequencies that the falling edges of both signals (clk _L sB, CUCXL _S B) may be distorted

(marked as grey). The SR-latch at the output of the LSB-modulator utilizes only the rising edges of the separate paths, and therefore may produce an output signal (out, outx) without the distortion. The SR-latch provides also differential output signaling. Utilizing the separate paths, the maximum operation frequency of the variable delay buffer may be increased.

[0055] The variable delay buffer, shown in Figure 3 a, may comprise two similar inverter stages whose delay is controlled with the LSB-control word CLSB- In order to achieve highly linear digital-to-delay conversion with constant step size, the delay is realized by controlling the capacitor load at the inverter output according to the CLSB- In addition to linear digital-to-delay conversion, the capacitor tuning achieves fine tuning resolution. The effect of variations in operating voltages, temperature, and components to the digital-to-delay conversion may be reduced or even eliminated with tunable inverters. In these inverters, the currents that charge and discharge the output capacitor may be controlled with digital control word CB. Instead of or in addition to the current based tuning, the variations may also be reduced or eliminated with capacitor tuning.

[0056] Figures 7a, 7b and 7c depict an example implementation of the variable delay buffer 324 at different levels. Figure 7a depicts a top-level circuit diagram of the example implementation. The variable delay buffer 324 may comprise a first variable delay inverter 600 and a second variable delay inverter 602. Delays of both these variable delay inverters 600, 602 are controlled by the synchronized LSB delay control from the first register 326a. Figure 7b depicts an example of one variable delay inverter which may be used in the variable delay buffer 324, and Figure 7c depicts a transistor-level circuit diagram of one variable delay inverter. In the example of Figure 7c the variable delay inverter comprises an input stage of a PMOS transistor 604 and an NMOS transistor 606 followed by a number of quadruples of MOS transistors 608, 609, 610, 611. The gates of the PMOS transistor 604 and the gate of the NMOS transistor 606 are coupled together and to the input 612. The drains of PMOS transistor 604 and the NMOS transistor 606 of the input stage are coupled together. The source of the PMOS transistor 604 may be coupled e.g. to a positive voltage supply and the source of the NMOS transistor 606 may be coupled e.g. to a negative voltage supply or to the ground. In this example embodiment each quadruple of MOS transistors 608, 609, 610, 611 comprises two PMOS transistors 608, 609 and two NMOS transistors 610, 611 connected in series. The gate of the first PMOS transistor 608 of each quadruple and the gate of the second NMOS transistor 611 of each quadruple are connected together and to the input. The gate of the second PMOS transistor 609 of each quadruple of MOS transistors is connected so that it receives one bit of a digital control word CB. The gate of the first NMOS transistor 609 of the corresponding quadruple of MOS transistors is connected so that it receives the same bit of a digital control word CB but as an inverted bit CBX. One purpose of the digital control word CB is to control currents that charge and discharge a variable output capacitor. The variable output capacitor may be implemented e.g. by using a set of MOSFETs 614 connected in series. The capacitances of the MOSFETs 612 may be designed so that each MOSFET has a capacitance which is about the power of two of the smallest capacitance of the MOSFETS. For example, the first MOSFET of the set 612 of MOSFETS has the capacitance C, the second MOSFET has the capacitance 2C, the second MOSFET has the capacitance 4C, etc. Hence, the total capacitance of the set of MOSFETS which is seen by the output of the variable delay inverter may be adjusted by providing the LSB-delay control information to the gates of the MOSFETs 612 in such a way that the least significant bit is provided to the gate of the MOSFET having the smallest capacitance C, the second least significant bit is provided to the gate of the MOSFET having the second smallest capacitance 2C, etc. Thus, the capacitance may be stepwise adjusted with substantially equally sized steps.

[0057] The number of quadruples of MOS transistors 608 and NMOS transistors 610 may be chosen to cover all delay variations due to possible variations in operating voltages, temperature, and components of the apparatus (process level).

[0058] It should be noted here that the above described implementation of the variable delay buffer 324 using mosfets is only an example embodiment and similar kind of operation may also be achieved by using different kinds of techniques, for example utilizing voltage controlled capacitors or other circuitry which provides means for implementing variable delay.

[0059] Figure 4 depicts an example of a part of a device 400, such as a wireless communications device (e.g., a cognitive radio/multi-radio device) that is constructed to include the frequency synthesizer 300 for generating one or more oscillator signals may be used. The device comprises one or more data processors 402 for controlling the operation of the device. The data processor 402 operates in accordance with program instructions stored in at least one storage medium, such as at least one memory 404. The data processor 402 sources control bus signals (cntr l, . . . ,cntr_n) to the frequency synthesizer 300 for setting individual ones of the output frequencies. These output frequencies form one or more local oscillator signals that may be applied simultaneously to an RF receiver circuitry 406. The RF receiver circuitry 406 may include one or multiple instances of filters, 406A, receivers 406B and mixers 406C. The receivers 406A may be configured to be connected with at least one, and possibly several antennas 407, and may operate to simultaneously receive and downconvert multiple reception channels in multiple frequency bands. The RF receiver circuitry 406 may be implemented e.g. as a single direct conversion receiver, as a plurality of direct conversion receivers, as a single superheterodyne-type receiver or as a plurality of superheterodyne-type receivers. In either case the downconverted signals from multiple reception channels are provided to at least one baseband circuitry block 408 to demodulate and decode received signaling and other data.

[0060] The device of Figure 4 also comprises an RF transmitter 410 for transmitting radio frequency signals. The transmitter 410 may comprise one or more mixers 41 OA adapted to receive signals to be transmitted and a local oscillator signal L02. The mixing result may be provided to a band pass filter 410B to filter out mixing results which are out of the transmission band, and an amplifier 4 IOC to amplify the RF signals before passing them to one or more antennas 407. The one or more antennas 407 may be the same one or more antennas than the RF receiver 406 uses or different antenna(s).

[0061] Note also that while shown in Figure 4 as generating a LOl signal for downconversion, the frequency synthesizer system 300 may be used as well for generating oscillator signals for use in IQ modulators/demodulators, analog-to-digital converters and/or digital-to-analog converters and/or synchronous digital logic.

[0062] The RF receiver circuitry 406 and/or the baseband circuitry 408 may be embodied as an integrated circuit. In some embodiments both the RF receiver circuitry 406 and the baseband circuitry 408 may be embodied in the same integrated circuit, and in some other embodiments they be embodied in different integrated circuits. The frequency synthesizer system 300 may be embodied as part of the RF receiver circuitry 406, or it may be embodied separately there from. In some embodiments all of the circuitry shown in Figure 4, including the data processor 402 and possibly also the memory 404, may be embodied in one integrated circuit module or package.

[0063] In some embodiments all or some of the functionality of the frequency synthesizer 300 may be embodied by the data processor 402 or by another data processor, such as a high speed digital signal processor operating under control of a stored program.

[0064] Note further that while shown in the context of a radio receiver, the exemplary embodiments may be used as well to provide local oscillator and other frequency signals for a radio frequency transmitter, such as upconversion local oscillator signals in a multi- transmitter type of device to an analog-to-digital converter, to a digital-to-analog converter, synchronous digital logic, and to other circuits in which adjustable frequency generation is used.

[0065] Figure 8 depicts as a flow diagram of an example method. In the method a reference clock signal is received 802 and a set of phase shifted reference clock signals are obtained 804. Also a phase selection control is obtained 806. A most significant part of the phase selection control is used to select one of the phase shifted reference clock signals 808; and a least significant part of the phase selection control is used to delay the selected phase shifted reference clock signal 810.

[0066] For demonstration purposes, Figure 9 depicts the simulated deterministic jitter and spectrum of the digital period synthesizer 302 output 314 and the LSB-modulator 300 output 332 with 5-bit LSB-modulator implementation with synchronization at f _out =2.155

GHz. The simulation results indicate that the synchronization may reduce quantization related noise. In this simulation the reduction was about 30 dB.

[0067] The following describes in further detail suitable apparatus and possible mechanisms for implementing the embodiments of the invention. In this regard reference is first made to Figure 10 which shows a schematic block diagram of an exemplary apparatus or electronic device 50 depicted in Figure 11, which may incorporate a receiver front end according to an embodiment of the invention.

[0068] The electronic device 50 may for example be a mobile terminal or user equipment of a wireless communication system. However, it would be appreciated that embodiments of the invention may be implemented within any electronic device or apparatus which may require reception of radio frequency signals and/or generation of clock signals for sampling and synchronization purposes.

[0069] The apparatus 50 may comprise a housing 30 for incorporating and protecting the device. The apparatus 50 further may comprise a display 32 in the form of a liquid crystal display. In other embodiments of the invention the display may be any suitable display technology suitable to display an image or video. The apparatus 50 may further comprise a keypad 34. In other embodiments of the invention any suitable data or user interface mechanism may be employed. For example the user interface may be

implemented as a virtual keyboard or data entry system as part of a touch-sensitive display. The apparatus may comprise a microphone 36 or any suitable audio input which may be a digital or analogue signal input. The apparatus 50 may further comprise an audio output device which in embodiments of the invention may be any one of: an earpiece 38, speaker, or an analogue audio or digital audio output connection. The apparatus 50 may also comprise a battery 40 (or in other embodiments of the invention the device may be powered by any suitable mobile energy device such as solar cell, fuel cell or clockwork generator). The apparatus may further comprise an infrared port 42 for short range line of sight communication to other devices. In other embodiments the apparatus 50 may further comprise any suitable short range communication solution such as for example a Bluetooth wireless connection or a USB/firewire wired connection.

[0070] The apparatus 50 may comprise a controller 56 or processor for controlling the apparatus 50. The controller 56 may be connected to memory 58 which in embodiments of the invention may store both data and/or may also store instructions for implementation on the controller 56. The controller 56 may further be connected to codec circuitry 54 suitable for carrying out coding and decoding of audio and/or video data or assisting in coding and decoding carried out by the controller 56.

[0071] The apparatus 50 may further comprise a card reader 48 and a smart card 46, for example a UICC and UICC reader for providing user information and being suitable for providing authentication information for authentication and authorization of the user at a network.

[0072] The apparatus 50 may comprise radio interface circuitry 52 connected to the controller and suitable for generating wireless communication signals for example for communication with a cellular communications network, a wireless communications system or a wireless local area network. The apparatus 50 may further comprise an antenna 102 connected to the radio interface circuitry 52 for transmitting radio frequency signals generated at the radio interface circuitry 52 to other apparatus(es) and for receiving radio frequency signals from other apparatus(es).

[0073] In some embodiments of the invention, the apparatus 50 comprises a camera capable of recording or detecting imaging.

[0074] With respect to Figure 12, an example of a system within which embodiments of the present invention can be utilized is shown. The system 10 comprises multiple communication devices which can communicate through one or more networks. The system 10 may comprise any combination of wired and/or wireless networks including, but not limited to a wireless cellular telephone network (such as a GSM, UMTS, CDMA network etc.), a wireless local area network (WLAN) such as defined by any of the IEEE 802.x standards, a Bluetooth personal area network, an Ethernet local area network, a token ring local area network, a wide area network, and the Internet.

[0075] For example, the system shown in Figure 12 shows a mobile telephone network 11 and a representation of the internet 28. Connectivity to the internet 28 may include, but is not limited to, long range wireless connections, short range wireless connections, and various wired connections including, but not limited to, telephone lines, cable lines, power lines, and similar communication pathways.

[0076] The example communication devices shown in the system 10 may include, but are not limited to, an electronic device or apparatus 50, a combination of a personal digital assistant (PDA) and a mobile telephone 14, a PDA 16, an integrated messaging device (IMD) 18, a desktop computer 20, a notebook computer 22. The apparatus 50 may be stationary or mobile when carried by an individual who is moving. The apparatus 50 may also be located in a mode of transport including, but not limited to, a car, a truck, a taxi, a bus, a train, a boat, an airplane, a bicycle, a motorcycle or any similar suitable mode of transport.

[0077] Some or further apparatus may send and receive calls and messages and communicate with service providers through a wireless connection 25 to a base station 24. The base station 24 may be connected to a network server 26 that allows communication between the mobile telephone network 11 and the internet 28. The system may include additional communication devices and communication devices of various types.

[0078] The communication devices may communicate using various transmission technologies including, but not limited to, code division multiple access (CDMA), global systems for mobile communications (GSM), universal mobile telecommunications system (UMTS), time divisional multiple access (TDMA), frequency division multiple access (FDMA), transmission control protocol-internet protocol (TCP-IP), short messaging service (SMS), multimedia messaging service (MMS), email, instant messaging service (IMS), Bluetooth, IEEE 802.11 and any similar wireless communication technology. A communications device involved in implementing various embodiments of the present invention may communicate using various media including, but not limited to, radio, infrared, laser, cable connections, and any suitable connection. In the following some example implementations of apparatuses utilizing the present invention will be described in more detail.

[0079] Although the above examples describe embodiments of the invention operating within a wireless communication device, it would be appreciated that the invention as described above may be implemented as a part of any apparatus comprising a circuitry in which radio frequency signals are transmitted and received. Thus, for example, embodiments of the invention may be implemented in a mobile phone, in a base station, in a computer such as a desktop computer or a tablet computer comprising radio frequency communication means (e.g. wireless local area network, cellular radio, etc.).

[0080] In general, the various embodiments of the invention may be implemented in hardware or special purpose circuits or any combination thereof. While various aspects of the invention may be illustrated and described as block diagrams or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

[0081] Embodiments of the inventions may be practiced in various components such as integrated circuit modules. The design of integrated circuits is by and large a highly automated process. Complex and powerful software tools are available for converting a logic level design into a semiconductor circuit design ready to be etched and formed on a semiconductor substrate.

[0082] Programs, such as those provided by Synopsys, Inc. of Mountain View,

California and Cadence Design, of San Jose, California automatically route conductors and locate components on a semiconductor chip using well established rules of design as well as libraries of pre stored design modules. Once the design for a semiconductor circuit has been completed, the resultant design, in a standardized electronic format (e.g., Opus, GDSII, or the like) may be transmitted to a semiconductor fabrication facility or "fab" for fabrication.

[0083] The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention.

[0084] In the following some examples will be provided.

[0085] According to a first example, there is provided a method comprising:

receiving a reference clock signal;

obtaining a set of phase shifted reference clock signals;

obtaining a phase selection control;

using a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

using a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0086] In some embodiments the method comprises:

delaying in a first delay path a rising edge of the selected phase shifted reference clock signal to obtain a rising edge of an output clock signal; and

delaying in a second delay path a falling edge of the selected phase shifted reference clock signal to obtain a falling edge of the output clock signal. [0087] In some embodiments the method comprises:

obtaining an inverted selected phase shifted reference clock signal; and

using the inverted selected phase shifted reference clock signal in the second delay path.

[0088] In some embodiments the method comprises at least one of the following:

using the output clock signal as a local oscillator signal for an RF mixer;

using the output clock signal as a clock signal for an analog-to-digital converter; using the output clock signal as a clock signal for a digital-to-analog converter; using the output clock signal as a clock signal for a synchronous digital logic.

[0089] In some embodiments the method comprises:

adding the phase selection control to a previous accumulated value when the selected phase shifted reference clock signal changes from a first state to a second state, wherein the accumulated value after the addition forms the phase selection control to be used in the selection of the next phase shifted reference clock signal.

[0090] According to a second example, there is provided an apparatus comprising: an input for receiving a reference clock signal;

a reference generator for obtaining a set of phase shifted reference clock signals; a phase accumulator for obtaining a phase selection control;

a phase selector adapted to use a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

a variable delay buffer adapted to use a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0091] According to a third example, there is provided an apparatus comprising at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

receive a reference clock signal;

obtain a set of phase shifted reference clock signals;

obtain a phase selection control;

use a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and use a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0092] In some embodiments of the apparatus said at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

delay in a first delay path a rising edge of the selected phase shifted reference clock signal to obtain a rising edge of an output clock signal; and

delay in a second delay path a falling edge of the selected phase shifted reference clock signal to obtain a falling edge of the output clock signal.

[0093] In some embodiments of the apparatus said at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

obtain an inverted selected phase shifted reference clock signal; and

use the inverted selected phase shifted reference clock signal in the second delay path.

[0094] In some embodiments of the apparatus said at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

use the output clock signal as a local oscillator signal for an RF mixer;

use the output clock signal as a clock signal for an analog-to-digital converter; use the output clock signal as a clock signal for a digital-to-analog converter; use the output clock signal as a clock signal for a synchronous digital logic.

[0095] In some embodiments of the apparatus said at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

add the phase selection control to a previous accumulated value when the selected phase shifted reference clock signal changes from a first state to a second state, wherein the accumulated value after the addition forms the phase selection control to be used in the selection of the next phase shifted reference clock signal. [0096] According to a fourth example, there is provided a computer program product including one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:

receive a reference clock signal;

obtain a set of phase shifted reference clock signals;

obtain a phase selection control;

use a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

use a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.

[0097] In some embodiments the computer program product includes one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:

delay in a first delay path a rising edge of the selected phase shifted reference clock signal to obtain a rising edge of an output clock signal; and

delay in a second delay path a falling edge of the selected phase shifted reference clock signal to obtain a falling edge of the output clock signal.

[0098] In some embodiments of the computer program product includes one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:

obtain an inverted selected phase shifted reference clock signal; and

use the inverted selected phase shifted reference clock signal in the second delay path.

[0099] In some embodiments of the computer program product includes one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:

use the output clock signal as a local oscillator signal for an RF mixer;

use the output clock signal as a clock signal for an analog-to-digital converter; use the output clock signal as a clock signal for a digital-to-analog converter; use the output clock signal as a clock signal for a synchronous digital logic. [0100] In some embodiments of the computer program product includes one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:

add the phase selection control to a previous accumulated value when the selected phase shifted reference clock signal changes from a first state to a second state, wherein the accumulated value after the addition forms the phase selection control to be used in the selection of the next phase shifted reference clock signal.

[0101] According to a fifth example, there is provided an apparatus comprising:

means for receiving a reference clock signal;

means for obtaining a set of phase shifted reference clock signals;

means for obtaining a phase selection control;

means for using a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and

means for using a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.