METHOD AND APPARATUS FOR INITIALIZING PREDICTOR PALETTE

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present disclosure claims priority to U.S. Provisional Application No.

62/955,522, filed on December 31, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

[0002] The present disclosure generally relates to video processing, and more particularly, to methods and apparatuses for signaling a predictor palette initializer and using the predictor palette initializer to initialize a predictor palette.

BACKGROUND

[0003] A video is a set of static pictures (or “frames”) capturing the visual information. To reduce the storage memory and the transmission bandwidth, a video can be compressed before storage or transmission and decompressed before display. The compression process is usually referred to as encoding and the decompression process is usually referred to as decoding. There are various video coding formats which use standardized video coding technologies, most commonly based on prediction, transform, quantization, entropy coding and in-loop filtering. The video coding standards, such as the

High Efficiency Video Coding (HEVC/H.265) standard, the Versatile Video Coding

(VVC/H.266) standard, AVS standards, specifying the specific video coding formats, are developed by standardization organizations. With more and more advanced video coding technologies being adopted in the video standards, the coding efficiency of the new video coding standards get higher and higher. SUMMARY OF THE DISCLOSURE

[0004] In some embodiments, an exemplary palette coding method includes: determining, based on a first flag, whether a first initial predictor palette is signaled in a predictor palette initializer; and in response to the first initial predictor palette being signaled in the predictor palette initializer, determining, based on a second flag, whether a second initial predictor palette and a third initial predictor palette are signaled in the predictor palette initializer.

[0005] In some embodiments, an exemplary video processing apparatus includes at least one memory for storing instructions and at least one processor. The at least one processor is configured to execute the instructions to cause the apparatus to perform: determining, based on a first flag, whether a first initial predictor palette is signaled in a predictor palette initializer; and in response to the first initial predictor palette being signaled in the predictor palette initializer, determining, based on a second flag, whether a second initial predictor palette and a third initial predictor palette are signaled in the predictor palette initializer.

[0006] In some embodiments, an exemplary non-transitory computer readable storage medium stores a set of instructions. The set of instructions are executable by one or more processing devices to cause a video processing apparatus to perform: determining, based on a first flag, whether a first initial predictor palette is signaled in a predictor palette initializer; and in response to the first initial predictor palette being signaled in the predictor palette initializer, determining, based on a second flag, whether a second initial predictor palette and a third initial predictor palette are signaled in the predictor palette initializer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying figures. Various features shown in the figures are not drawn to scale.

[0008] FIG. 1 is a schematic diagram illustrating structures of an example video sequence, according to some embodiments of the present disclosure.

[0009] FIG. 2A is a schematic diagram illustrating an exemplary encoding process of a hybrid video coding system, consistent with embodiments of the disclosure.

[0010] FIG. 2B is a schematic diagram illustrating another exemplary encoding process of a hybrid video coding system, consistent with embodiments of the disclosure.

[0011] FIG. 3A is a schematic diagram illustrating an exemplary decoding process of a hybrid video coding system, consistent with embodiments of the disclosure.

[0012] FIG. 3B is a schematic diagram illustrating another exemplary decoding process of a hybrid video coding system, consistent with embodiments of the disclosure.

[0013] FIG. 4 is a block diagram of an exemplary apparatus for encoding or decoding a video, according to some embodiments of the present disclosure.

[0014] FIG. 5 illustrates a schematic diagram of an exemplary block coded in palette mode, according to some embodiments of the present disclosure.

[0015] FIG. 6 illustrates a schematic diagram of an exemplary process for updating predictor palette after encoding a coding unit, according to some embodiments of the present disclosure.

[0016] FIG. 7 illustrates an example of partitioning a picture into multiple coding tree units (CTUs), according to some embodiments of the present disclosure.

[0017] FIG. 8 illustrates an example of partitioning a picture in the raster-scan slice mode, according to some embodiments of the present disclosure. [0018] FIG. 9 illustrates an example of partitioning a picture in the rectangular slice mode, according to some embodiments of the present disclosure.

[0019] FIG. 10 illustrates an example of a picture partitioned into tiles and rectangular slices, according to some embodiments of the present disclosure.

[0020] FIG. 11 illustrates an exemplary Table 1 showing an exemplary predictor palette initializer syntax structure, according to some embodiments of the present disclosure.

[0021 ] FIG. 12 illustrates an exemplary Table 2 showing another exemplary predictor palette initializer syntax structure, according to some embodiments of the present disclosure.

[0022] FIG. 13 illustrates an exemplary Table 3 showing another exemplary predictor palette initializer syntax structure, according to some embodiments of the present disclosure.

[0023] FIG. 14 illustrates an exemplary Table 4 showing an exemplary adaption parameter set (APS) syntax structure for signaling predictor palette initializer, according to some embodiments of the present disclosure.

[0024] FIG. 15 illustrates an exemplary Table 5 showing an exemplary picture header (PH) syntax structure for referencing to predictor palette initializer in APS, according to some embodiments of the present disclosure.

[0025] FIG. 16 illustrates an exemplary Table 6 showing an exemplary picture header syntax structure for signaling predictor palette initializer, according to some embodiments of the present disclosure.

[0026] FIG. 17 illustrates an exemplary Table 7 showing an exemplary predictor palette initialization process, according to some embodiments of the present disclosure. [0027] FIG. 18 illustrates an exemplary Table 8 showing another exemplary predictor palette initialization process, according to some embodiments of the present disclosure.

[0028] FIG. 19 illustrates a flowchart of an exemplary palette coding method, according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

[0029] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the invention. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the invention as recited in the appended claims. Particular aspects of the present disclosure are described in greater detail below. The terms and definitions provided herein control, if in conflict with terms and/or definitions incorporated by reference.

[0030] The Joint Video Experts Team (JVET) of the ITU-T Video Coding Expert

Group (ITU-T VCEG) and the ISO/IEC Moving Picture Expert Group (ISO/IEC MPEG) is currently developing the Versatile Video Coding (VVC/H.266) standard. The VVC standard is aimed at doubling the compression efficiency of its predecessor, the High Efficiency Video

Coding (HEVC/H.265) standard. In other words, VVC’s goal is to achieve the same subjective quality as HEVC/H.265 using half the bandwidth.

[0031] In order to achieve the same subjective quality as HEVC/H.265 using half the bandwidth, the JVET has been developing technologies beyond HEVC using the joint exploration model (JEM) reference software. As coding technologies were incorporated into the JEM, the JEM achieved substantially higher coding performance than HEVC.

[0032] The VVC standard has been developed recent, and continues to include more coding technologies that provide better compression performance. VVC is based on the same hybrid video coding system that has been used in modem video compression standards such as HEVC, H.264/AVC, MPEG2, H.263, etc.

[0033] A video is a set of static pictures (or “frames”) arranged in a temporal sequence to store visual information. A video capture device (e.g., a camera) can be used to capture and store those pictures in a temporal sequence, and a video playback device (e.g., a television, a computer, a smartphone, a tablet computer, a video player, or any end-user terminal with a function of display) can be used to display such pictures in the temporal sequence. Also, in some applications, a video capturing device can transmit the captured video to the video playback device (e.g., a computer with a monitor) in real-time, such as for surveillance, conferencing, or live broadcasting.

[0034] For reducing the storage space and the transmission bandwidth needed by such applications, the video can be compressed before storage and transmission and decompressed before the display. The compression and decompression can be implemented by software executed by a processor (e.g., a processor of a generic computer) or specialized hardware.

The module for compression is generally referred to as an “encoder,” and the module for decompression is generally referred to as a “decoder.” The encoder and decoder can be collectively referred to as a “codec.” The encoder and decoder can be implemented as any of a variety of suitable hardware, software, or a combination thereof. For example, the hardware implementation of the encoder and decoder can include circuitry, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits

(ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combinations thereof. The software implementation of the encoder and decoder can include program codes, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process fixed in a computer-readable medium. Video compression and decompression can be implemented by various algorithms or standards, such as MPEG- 1, MPEG-2, MPEG-4,

H.26x series, or the like. In some applications, the codec can decompress the video from a first coding standard and re-compress the decompressed video using a second coding standard, in which case the codec can be referred to as a “transcoder.”

[0035] The video encoding process can identify and keep useful information that can be used to reconstruct a picture and disregard unimportant information for the reconstruction.

If the disregarded, unimportant information cannot be fully reconstructed, such an encoding process can be referred to as “lossy.” Otherwise, it can be referred to as “lossless." Most encoding processes are lossy, which is a tradeoff to reduce the needed storage space and the transmission bandwidth.

[0036] The useful information of a picture being encoded (referred to as a “current picture”) include changes with respect to a reference picture (e.g., a picture previously encoded and reconstructed). Such changes can include position changes, luminosity changes, or color changes of the pixels, among which the position changes are mostly concerned.

Position changes of a group of pixels that represent an object can reflect the motion of the object between the reference picture and the current picture.

[0037] A picture coded without referencing another picture (i.e., it is its own reference picture) is referred to as an “I-picture.” A picture coded using a previous picture as a reference picture is referred to as a “P-picture.” A picture coded using both a previous picture and a future picture as reference pictures (i.e., the reference is “bi-directional”) is referred to as a “B-picture.” [0038] FIG. 1 illustrates structures of an example video sequence 100, according to some embodiments of the present disclosure. Video sequence 100 can be a live video or a video having been captured and archived. Video 100 can be a real-life video, a computer- generated video (e.g., computer game video), or a combination thereof (e.g., a real-life video with augmented-reality effects). Video sequence 100 can be inputted from a video capture device (e.g., a camera), a video archive (e.g., a video file stored in a storage device) containing previously captured video, or a video feed interface (e.g., a video broadcast transceiver) to receive video from a video content provider.

[0039] As shown in FIG. 1, video sequence 100 can include a series of pictures arranged temporally along a timeline, including pictures 102, 104, 106, and 108. Pictures

102-106 are continuous, and there are more pictures between pictures 106 and 108. In FIG.

1, picture 102 is an I-picture, the reference picture of which is picture 102 itself. Picture 104 is a P-picture, the reference picture of which is picture 102, as indicated by the arrow. Picture

106 is a B-picture, the reference pictures of which are pictures 104 and 108, as indicated by the arrows. In some embodiments, the reference picture of a picture (e.g., picture 104) can be not immediately preceding or following the picture. For example, the reference picture of picture 104 can be a picture preceding picture 102. It should be noted that the reference pictures of pictures 102-106 are only examples, and the present disclosure does not limit embodiments of the reference pictures as the examples shown in FIG. 1.

[0040] Typically, video codecs do not encode or decode an entire picture at one time due to the computing complexity of such tasks. Rather, they can split the picture into basic segments, and encode or decode the picture segment by segment. Such basic segments are referred to as basic processing units (“BPUs”) in the present disclosure. For example, structure 110 in FIG. 1 shows an example structure of a picture of video sequence 100 (e.g., any of pictures 102-108). In structure 110, a picture is divided into 4x4 basic processing units, the boundaries of which are shown as dash lines. In some embodiments, the basic processing units can be referred to as “macroblocks” in some video coding standards (e.g.,

MPEG family, H.261, H.263, or H.264/AVC), or as “coding tree units” (“CTUs”) in some other video coding standards (e.g., H.265ZHEVC or H.266/VVC). The basic processing units can have variable sizes in a picture, such as 128x128, 64x64, 32x32, 16x16, 4x8, 16x32, or any arbitrary shape and size of pixels. The sizes and shapes of the basic processing units can be selected for a picture based on the balance of coding efficiency and levels of details to be kept in the basic processing unit.

[0041] The basic processing units can be logical units, which can include a group of different types of video data stored in a computer memory (e.g., in a video frame buffer). For example, a basic processing unit of a color picture can include a luma component (Y) representing achromatic brightness information, one or more chroma components (e.g., Cb and Cr) representing color information, and associated syntax elements, in which the luma and chroma components can have the same size of the basic processing unit. The luma and chroma components can be referred to as “coding tree blocks” (“CTBs”) in some video coding standards (e.g., H.265/HEVC or H.266/VVC). Any operation performed to a basic processing unit can be repeatedly performed to each of its luma and chroma components.

[0042] Video coding has multiple stages of operations, examples of which are shown in FIGs. 2A-2B and FIGs. 3A-3B. For each stage, the size of the basic processing units can still be too large for processing, and thus can be further divided into segments referred to as

“basic processing sub-units” in the present disclosure. In some embodiments, the basic processing sub-units can be referred to as “blocks” in some video coding standards (e.g.,

MPEG family, H.261, H.263, or H.264/AVC), or as “coding units” (“CUs”) in some other video coding standards (e.g., H.265/HEVC or H.266/VVC). A basic processing sub-unit can have the same or smaller size than the basic processing unit. Similar to the basic processing units, basic processing sub-units are also logical units, which can include a group of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in a computer memory (e.g., in a video frame buffer). Any operation performed to a basic processing sub- unit can be repeatedly performed to each of its luma and chroma components. It should be noted that such division can be performed to further levels depending on processing needs. It should also be noted that different stages can divide the basic processing units using different schemes.

[0043] For example, at a mode decision stage (an example of which is shown in FIG.

2B), the encoder can decide what prediction mode (e.g., intra-picture prediction or inter- picture prediction) to use for a basic processing unit, which can be too large to make such a decision. The encoder can split the basic processing unit into multiple basic processing sub- units (e.g., CUs as in H.265/HEVC or H.266/VVC), and decide a prediction type for each individual basic processing sub-unit.

[0044] For another example, at a prediction stage (an example of which is shown in

FIGs. 2A-2B), the encoder can perform prediction operation at the level of basic processing sub-units (e.g., CUs). However, in some cases, a basic processing sub-unit can still be too large to process. The encoder can further split the basic processing sub-unit into smaller segments (e.g., referred to as “prediction blocks” or “PBs” in H.265/HEVC or H.266/VVC), at the level of which the prediction operation can be performed.

[0045] For another example, at a transform stage (an example of which is shown in

FIGs. 2A-2B), the encoder can perform a transform operation for residual basic processing sub-units (e.g., CUs). However, in some cases, a basic processing sub-unit can still be too large to process. The encoder can further split the basic processing sub-unit into smaller segments (e.g., referred to as “transform blocks” or “TBs” in H.265/HEVC or H.266/VVC), at the level of which the transform operation can be performed. It should be noted that the division schemes of the same basic processing sub-unit can be different at the prediction stage and the transform stage. For example, in H.265/HEVC or H.266/VVC, the prediction blocks and transform blocks of the same CU can have different sizes and numbers.

[0046] In structure 110 of FIG. 1, basic processing unit 112 is further divided into

3x3 basic processing sub-units, the boundaries of which are shown as dotted lines. Different basic processing units of the same picture can be divided into basic processing sub-units in different schemes.

[0047] In some implementations, to provide the capability of parallel processing and error resilience to video encoding and decoding, a picture can be divided into regions for processing, such that, for a region of the picture, the encoding or decoding process can depend on no information from any other region of the picture. In other words, each region of the picture can be processed independently. By doing so, the codec can process different regions of a picture in parallel, thus increasing the coding efficiency. Also, when data of a region is corrupted in the processing or lost in network transmission, the codec can correctly encode or decode other regions of the same picture without reliance on the corrupted or lost data, thus providing the capability of error resilience. In some video coding standards, a picture can be divided into different types of regions. For example, H.265/HEVC and

H.266/VVC provide two types of regions: “slices” and “tiles.” It should also be noted that different pictures of video sequence 100 can have different partition schemes for dividing a picture into regions.

[0048] For example, in FIG. 1, structure 110 is divided into three regions 114, 116, and 118, the boundaries of which are shown as solid lines inside structure 110. Region 114 includes four basic processing units. Each of regions 116 and 118 includes six basic processing units. It should be noted that the basic processing units, basic processing sub- units, and regions of structure 110 in FIG. 1 are only examples, and the present disclosure does not limit embodiments thereof.

[0049] FIG. 2A illustrates a schematic diagram of an example encoding process

200 A, consistent with embodiments of the disclosure. For example, the encoding process

200A can be performed by an encoder. As shown in FIG. 2A, the encoder can encode video sequence 202 into video bitstream 228 according to process 200 A. Similar to video sequence

100 in FIG. 1, video sequence 202 can include a set of pictures (referred to as “original pictures”) arranged in a temporal order. Similar to structure 110 in FIG. 1, each original picture of video sequence 202 can be divided by the encoder into basic processing units, basic processing sub-units, or regions for processing. In some embodiments, the encoder can perform process 200A at the level of basic processing units for each original picture of video sequence 202. For example, the encoder can perform process 200A in an iterative manner, in which the encoder can encode a basic processing unit in one iteration of process 200 A. In some embodiments, the encoder can perform process 200 A in parallel for regions (e.g., regions 114-118) of each original picture of video sequence 202.

[0050] In FIG. 2A, the encoder can feed a basic processing unit (referred to as an

“original BPU”) of an original picture of video sequence 202 to prediction stage 204 to generate prediction data 206 and predicted BPU 208. The encoder can subtract predicted

BPU 208 from the original BPU to generate residual BPU 210. The encoder can feed residual

BPU 210 to transform stage 212 and quantization stage 214 to generate quantized transform coefficients 216. The encoder can feed prediction data 206 and quantized transform coefficients 216 to binary coding stage 226 to generate video bitstream 228. Components

202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 can be referred to as a “forward path.”

During process 200 A, after quantization stage 214, the encoder can feed quantized transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate reconstructed residual BPU 222. The encoder can add reconstructed residual BPU 222 to predicted BPU 208 to generate prediction reference 224, which is used in prediction stage

204 for the next iteration of process 200 A. Components 218, 220, 222, and 224 of process

200A can be referred to as a “reconstruction path.” The reconstruction path can be used to ensure that both the encoder and the decoder use the same reference data for prediction.

[0051] The encoder can perform process 200 A iteratively to encode each original

BPU of the original picture (in the forward path) and generate predicted reference 224 for encoding the next original BPU of the original picture (in the reconstruction path). After encoding all original BPUs of the original picture, the encoder can proceed to encode the next picture in video sequence 202.

[0052] Referring to process 200A, the encoder can receive video sequence 202 generated by a video capturing device (e.g., a camera). The term “receive” used herein can refer to receiving, inputting, acquiring, retrieving, obtaining, reading, accessing, or any action in any manner for inputting data.

[0053] At prediction stage 204, at a current iteration, the encoder can receive an original BPU and prediction reference 224, and perform a prediction operation to generate prediction data 206 and predicted BPU 208. Prediction reference 224 can be generated from the reconstruction path of the previous iteration of process 200 A. The purpose of prediction stage 204 is to reduce information redundancy by extracting prediction data 206 that can be used to reconstruct the original BPU as predicted BPU 208 from prediction data 206 and prediction reference 224.

[0054] Ideally, predicted BPU 208 can be identical to the original BPU. However, due to non-ideal prediction and reconstruction operations, predicted BPU 208 is generally slightly different from the original BPU. For recording such differences, after generating predicted BPU 208, the encoder can subtract it from the original BPU to generate residual BPU 210. For example, the encoder can subtract values (e.g., greyscale values or RGB values) of pixels of predicted BPU 208 from values of corresponding pixels of the original

BPU. Each pixel of residual BPU 210 can have a residual value as a result of such subtraction between the corresponding pixels of the original BPU and predicted BPU 208. Compared with the original BPU, prediction data 206 and residual BPU 210 can have fewer bits, but they can be used to reconstruct the original BPU without significant quality deterioration.

Thus, the original BPU is compressed.

[0055] To further compress residual BPU 210, at transform stage 212, the encoder can reduce spatial redundancy of residual BPU 210 by decomposing it into a set of two- dimensional “base patterns,” each base pattern being associated with a “transform coefficient.” The base patterns can have the same size (e.g., the size of residual BPU 210).

Each base pattern can represent a variation frequency (e.g., frequency of brightness variation) component of residual BPU 210. None of the base patterns can be reproduced from any combinations (e.g., linear combinations) of any other base patterns. In other words, the decomposition can decompose variations of residual BPU 210 into a frequency domain. Such a decomposition is analogous to a discrete Fourier transform of a function, in which the base patterns are analogous to the base functions (e.g., trigonometry functions) of the discrete

Fourier transform, and the transform coefficients are analogous to the coefficients associated with the base functions.

[0056] Different transform algorithms can use different base patterns. Various transform algorithms can be used at transform stage 212, such as, for example, a discrete cosine transform, a discrete sine transform, or the like. The transform at transform stage 212 is invertible. That is, the encoder can restore residual BPU 210 by an inverse operation of the transform (referred to as an “inverse transform”). For example, to restore a pixel of residual

BPU 210, the inverse transform can be multiplying values of corresponding pixels of the base patterns by respective associated coefficients and adding the products to produce a weighted sum. For a video coding standard, both the encoder and decoder can use the same transform algorithm (thus the same base patterns). Thus, the encoder can record only the transform coefficients, from which the decoder can reconstruct residual BPU 210 without receiving the base patterns from the encoder. Compared with residual BPU 210, the transform coefficients can have fewer bits, but they can be used to reconstruct residual BPU 210 without significant quality deterioration. Thus, residual BPU 210 is further compressed.

[0057] The encoder can further compress the transform coefficients at quantization stage 214. In the transform process, different base patterns can represent different variation frequencies (e.g., brightness variation frequencies). Because human eyes are generally better at recognizing low-frequency variation, the encoder can disregard information of high- frequency variation without causing significant quality deterioration in decoding. For example, at quantization stage 214, the encoder can generate quantized transform coefficients

216 by dividing each transform coefficient by an integer value (referred to as a “quantization parameter”) and rounding the quotient to its nearest integer. After such an operation, some transform coefficients of the high-frequency base patterns can be converted to zero, and the transform coefficients of the low-frequency base patterns can be converted to smaller integers. The encoder can disregard the zero-value quantized transform coefficients 216, by which the transform coefficients are further compressed. The quantization process is also invertible, in which quantized transform coefficients 216 can be reconstructed to the transform coefficients in an inverse operation of the quantization (referred to as “inverse quantization”).

[0058] Because the encoder disregards the remainders of such divisions in the rounding operation, quantization stage 214 can be lossy. Typically, quantization stage 214 can contribute the most information loss in process 200A. The larger the information loss is, the fewer bits the quantized transform coefficients 216 can need. For obtaining different levels of information loss, the encoder can use different values of the quantization parameter or any other parameter of the quantization process.

[0059] At binary coding stage 226, the encoder can encode prediction data 206 and quantized transform coefficients 216 using a binary coding technique, such as, for example, entropy coding, variable length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm. In some embodiments, besides prediction data 206 and quantized transform coefficients 216, the encoder can encode other information at binary coding stage 226, such as, for example, a prediction mode used at prediction stage 204, parameters of the prediction operation, a transform type at transform stage 212, parameters of the quantization process (e.g., quantization parameters), an encoder control parameter (e.g., a bitrate control parameter), or the like. The encoder can use the output data of binary coding stage 226 to generate video bitstream 228. In some embodiments, video bitstream 228 can be further packetized for network transmission.

[0060] Referring to the reconstruction path of process 200A, at inverse quantization stage 218, the encoder can perform inverse quantization on quantized transform coefficients

216 to generate reconstructed transform coefficients. At inverse transform stage 220, the encoder can generate reconstructed residual BPU 222 based on the reconstructed transform coefficients. The encoder can add reconstructed residual BPU 222 to predicted BPU 208 to generate prediction reference 224 that is to be used in the next iteration of process 200A.

[0061] It should be noted that other variations of the process 200A can be used to encode video sequence 202. In some embodiments, stages of process 200A can be performed by the encoder in different orders. In some embodiments, one or more stages of process 200A can be combined into a single stage. In some embodiments, a single stage of process 200A can be divided into multiple stages. For example, transform stage 212 and quantization stage

214 can be combined into a single stage. In some embodiments, process 200 A can include additional stages. In some embodiments, process 200A can omit one or more stages in FIG.

2A.

[0062] FIG. 2B illustrates a schematic diagram of another example encoding process

200B, consistent with embodiments of the disclosure. Process 200B can be modified from process 200 A. For example, process 200B can be used by an encoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared with process 200A, the forward path of process 200B additionally includes mode decision stage 230 and divides prediction stage 204 into spatial prediction stage 2042 and temporal prediction stage 2044. The reconstruction path of process 200B additionally includes loop filter stage 232 and buffer 234.

[0063] Generally, prediction techniques can be categorized into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., an intra-picture prediction or

“intra prediction”) can use pixels from one or more already coded neighboring BPUs in the same picture to predict the current BPU. That is, prediction reference 224 in the spatial prediction can include the neighboring BPUs. The spatial prediction can reduce the inherent spatial redundancy of the picture. Temporal prediction (e.g., an inter-picture prediction or

“inter prediction”) can use regions from one or more already coded pictures to predict the current BPU. That is, prediction reference 224 in the temporal prediction can include the coded pictures. The temporal prediction can reduce the inherent temporal redundancy of the pictures.

[0064] Referring to process 200B, in the forward path, the encoder performs the prediction operation at spatial prediction stage 2042 and temporal prediction stage 2044. For example, at spatial prediction stage 2042, the encoder can perform the intra prediction. For an original BPU of a picture being encoded, prediction reference 224 can include one or more neighboring BPUs that have been encoded (in the forward path) and reconstructed (in the reconstructed path) in the same picture. The encoder can generate predicted BPU 208 by extrapolating the neighboring BPUs. The extrapolation technique can include, for example, a linear extrapolation or interpolation, a polynomial extrapolation or interpolation, or the like.

In some embodiments, the encoder can perform the extrapolation at the pixel level, such as by extrapolating values of corresponding pixels for each pixel of predicted BPU 208. The neighboring BPUs used for extrapolation can be located with respect to the original BPU from various directions, such as in a vertical direction (e.g., on top of the original BPU), a horizontal direction (e.g., to the left of the original BPU), a diagonal direction (e.g., to the down-left, down-right, up-left, or up-right of the original BPU), or any direction defined in the used video coding standard. For the intra prediction, prediction data 206 can include, for example, locations (e.g., coordinates) of the used neighboring BPUs, sizes of the used neighboring BPUs, parameters of the extrapolation, a direction of the used neighboring BPUs with respect to the original BPU, or the like.

[0065] For another example, at temporal prediction stage 2044, the encoder can perform the inter prediction. For an original BPU of a current picture, prediction reference

224 can include one or more pictures (referred to as “reference pictures”) that have been encoded (in the forward path) and reconstructed (in the reconstructed path). In some embodiments, a reference picture can be encoded and reconstructed BPU by BPU. For example, the encoder can add reconstructed residual BPU 222 to predicted BPU 208 to generate a reconstructed BPU. When all reconstructed BPUs of the same picture are generated, the encoder can generate a reconstructed picture as a reference picture. The encoder can perform an operation of “motion estimation” to search for a matching region in a scope (referred to as a “search window”) of the reference picture. The location of the search window in the reference picture can be determined based on the location of the original BPU in the current picture. For example, the search window can be centered at a location having the same coordinates in the reference picture as the original BPU in the current picture and can be extended out for a predetermined distance. When the encoder identifies (e.g., by using a pel-recursive algorithm, a block-matching algorithm, or the like) a region similar to the original BPU in the search window, the encoder can determine such a region as the matching region. The matching region can have different dimensions (e.g., being smaller than, equal to, larger than, or in a different shape) from the original BPU. Because the reference picture and the current picture are temporally separated in the timeline (e.g., as shown in FIG. 1), it can be deemed that the matching region “moves” to the location of the original BPU as time goes by. The encoder can record the direction and distance of such a motion as a “motion vector.”

When multiple reference pictures are used (e.g., as picture 106 in FIG. 1), the encoder can search for a matching region and determine its associated motion vector for each reference picture. In some embodiments, the encoder can assign weights to pixel values of the matching regions of respective matching reference pictures.

[0066] The motion estimation can be used to identify various types of motions, such as, for example, translations, rotations, zooming, or the like. For inter prediction, prediction data 206 can include, for example, locations (e.g., coordinates) of the matching region, the motion vectors associated with the matching region, the number of reference pictures, weights associated with the reference pictures, or the like.

[0067] For generating predicted BPU 208, the encoder can perform an operation of

“motion compensation.” The motion compensation can be used to reconstruct predicted BPU

208 based on prediction data 206 (e.g., the motion vector) and prediction reference 224. For example, the encoder can move the matching region of the reference picture according to the motion vector, in which the encoder can predict the original BPU of the current picture.

When multiple reference pictures are used (e.g., as picture 106 in FIG. 1), the encoder can move the matching regions of the reference pictures according to the respective motion vectors and average pixel values of the matching regions. In some embodiments, if the encoder has assigned weights to pixel values of the matching regions of respective matching reference pictures, the encoder can add a weighted sum of the pixel values of the moved matching regions.

[0068] In some embodiments, the inter prediction can be unidirectional or bidirectional. Unidirectional inter predictions can use one or more reference pictures in the same temporal direction with respect to the current picture. For example, picture 104 in FIG.

1 is a uni directional inter-predicted picture, in which the reference picture (i.e., picture 102) precedes picture 104. Bidirectional inter predictions can use one or more reference pictures at both temporal directions with respect to the current picture. For example, picture 106 in FIG.

1 is a bidirectional inter-predicted picture, in which the reference pictures (i.e., pictures 104 and 108) are at both temporal directions with respect to picture 104.

[0069] Still referring to the forward path of process 200B, after spatial prediction

2042 and temporal prediction stage 2044, at mode decision stage 230, the encoder can select a prediction mode (e.g., one of the intra prediction or the inter prediction) for the current iteration of process 200B. For example, the encoder can perform a rate-distortion optimization technique, in which the encoder can select a prediction mode to minimize a value of a cost function depending on a bit rate of a candidate prediction mode and distortion of the reconstructed reference picture under the candidate prediction mode. Depending on the selected prediction mode, the encoder can generate the corresponding predicted BPU 208 and predicted data 206.

[0070] In the reconstruction path of process 200B, if intra prediction mode has been selected in the forward path, after generating prediction reference 224 (e.g., the current BPU that has been encoded and reconstructed in the current picture), the encoder can directly feed prediction reference 224 to spatial prediction stage 2042 for later usage (e.g., for extrapolation of a next BPU of the current picture). If the inter prediction mode has been selected in the forward path, after generating prediction reference 224 (e.g., the current picture in which all BPUs have been encoded and reconstructed), the encoder can feed prediction reference 224 to loop filter stage 232, at which the encoder can apply a loop filter to prediction reference 224 to reduce or eliminate distortion (e.g., blocking artifacts) introduced by the inter prediction. The encoder can apply various loop filter techniques at loop filter stage 232, such as, for example, deblocking, sample adaptive offsets, adaptive loop filters, or the like. The loop-filtered reference picture can be stored in buffer 234 (or

“decoded picture buffer”) for later use (e.g., to be used as an inter-prediction reference picture for a future picture of video sequence 202). The encoder can store one or more reference pictures in buffer 234 to be used at temporal prediction stage 2044. In some embodiments, the encoder can encode parameters of the loop filter (e.g., a loop filter strength) at binary coding stage 226, along with quantized transform coefficients 216, prediction data 206, and other information.

[0071] FIG. 3A illustrates a schematic diagram of an example decoding process

300 A, consistent with embodiments of the disclosure. Process 300 A can be a decompression process corresponding to the compression process 200A in FIG. 2A. In some embodiments, process 300 A can be similar to the reconstruction path of process 200 A. A decoder can decode video bitstream 228 into video stream 304 according to process 300 A. Video stream

304 can be very similar to video sequence 202. However, due to the information loss in the compression and decompression process (e.g., quantization stage 214 in FIGs. 2A-2B), generally, video stream 304 is not identical to video sequence 202. Similar to processes 200A and 200B in FIGs. 2A-2B, the decoder can perform process 300 A at the level of basic processing units (BPUs) for each picture encoded in video bitstream 228. For example, the decoder can perform process 300 A in an iterative manner, in which the decoder can decode a basic processing unit in one iteration of process 300 A. In some embodiments, the decoder can perform process 300A in parallel for regions (e.g., regions 114-118) of each picture encoded in video bitstream 228.

[0072] In FIG. 3A, the decoder can feed a portion of video bitstream 228 associated with a basic processing unit (referred to as an “encoded BPU”) of an encoded picture to binary decoding stage 302. At binary decoding stage 302, the decoder can decode the portion into prediction data 206 and quantized transform coefficients 216. The decoder can feed quantized transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate reconstructed residual BPU 222. The decoder can feed prediction data

206 to prediction stage 204 to generate predicted BPU 208. The decoder can add reconstructed residual BPU 222 to predicted BPU 208 to generate predicted reference 224. In some embodiments, predicted reference 224 can be stored in a buffer (e.g., a decoded picture buffer in a computer memory). The decoder can feed predicted reference 224 to prediction stage 204 for performing a prediction operation in the next iteration of process 300A.

[0073] The decoder can perform process 300A iteratively to decode each encoded

BPU of the encoded picture and generate predicted reference 224 for encoding the next encoded BPU of the encoded picture. After decoding all encoded BPUs of the encoded picture, the decoder can output the picture to video stream 304 for display and proceed to decode the next encoded picture in video bitstream 228.

[0074] At binary decoding stage 302, the decoder can perform an inverse operation of the binary coding technique used by the encoder (e.g., entropy coding, variable length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless compression algorithm). In some embodiments, besides prediction data 206 and quantized transform coefficients 216, the decoder can decode other information at binary decoding stage 302, such as, for example, a prediction mode, parameters of the prediction operation, a transform type, parameters of the quantization process (e.g., quantization parameters), an encoder control parameter (e.g., a bitrate control parameter), or the like. In some embodiments, if video bitstream 228 is transmitted over a network in packets, the decoder can depacketize video bitstream 228 before feeding it to binary decoding stage 302.

[0075] FIG. 3B illustrates a schematic diagram of another example decoding process

300B, consistent with embodiments of the disclosure. Process 300B can be modified from process 300A. For example, process 300B can be used by a decoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared with process 300 A, process 300B additionally divides prediction stage 204 into spatial prediction stage 2042 and temporal prediction stage 2044, and additionally includes loop filter stage 232 and buffer 234.

[0076] In process 300B, for an encoded basic processing unit (referred to as a

“current BPU”) of an encoded picture (referred to as a “current picture”) that is being decoded, prediction data 206 decoded from binary decoding stage 302 by the decoder can include various types of data, depending on what prediction mode was used to encode the current BPU by the encoder. For example, if intra prediction was used by the encoder to encode the current BPU, prediction data 206 can include a prediction mode indicator (e.g., a flag value) indicative of the intra prediction, parameters of the intra prediction operation, or the like. The parameters of the intra prediction operation can include, for example, locations

(e.g., coordinates) of one or more neighboring BPUs used as a reference, sizes of the neighboring BPUs, parameters of extrapolation, a direction of the neighboring BPUs with respect to the original BPU, or the like. For another example, if inter prediction was used by the encoder to encode the current BPU, prediction data 206 can include a prediction mode indicator (e.g., a flag value) indicative of the inter prediction, parameters of the inter prediction operation, or the like. The parameters of the inter prediction operation can include, for example, the number of reference pictures associated with the current BPU, weights respectively associated with the reference pictures, locations (e.g., coordinates) of one or more matching regions in the respective reference pictures, one or more motion vectors respectively associated with the matching regions, or the like.

[0077] Based on the prediction mode indicator, the decoder can decide whether to perform a spatial prediction (e.g., the intra prediction) at spatial prediction stage 2042 or a temporal prediction (e.g., the inter prediction) at temporal prediction stage 2044. The details of performing such spatial prediction or temporal prediction are described in FIG. 2B and will not be repeated hereinafter. After performing such spatial prediction or temporal prediction, the decoder can generate predicted BPU 208. The decoder can add predicted BPU

208 and reconstructed residual BPU 222 to generate prediction reference 224, as described in

FIG. 3A.

[0078] In process 300B, the decoder can feed predicted reference 224 to spatial prediction stage 2042 or temporal prediction stage 2044 for performing a prediction operation in the next iteration of process 300B. For example, if the current BPU is decoded using the intra prediction at spatial prediction stage 2042, after generating prediction reference 224

(e.g., the decoded current BPU), the decoder can directly feed prediction reference 224 to spatial prediction stage 2042 for later usage (e.g., for extrapolation of a next BPU of the current picture). If the current BPU is decoded using the inter prediction at temporal prediction stage 2044, after generating prediction reference 224 (e.g., a reference picture in which all BPUs have been decoded), the encoder can feed prediction reference 224 to loop filter stage 232 to reduce or eliminate distortion (e.g., blocking artifacts). The decoder can apply a loop filter to prediction reference 224, in a way as described in FIG. 2B. The loop- filtered reference picture can be stored in buffer 234 (e.g., a decoded picture buffer in a computer memory) for later use (e.g., to be used as an inter-prediction reference picture for a future encoded picture of video bitstream 228). The decoder can store one or more reference pictures in buffer 234 to be used at temporal prediction stage 2044. In some embodiments, when the prediction mode indicator of prediction data 206 indicates that inter prediction was used to encode the current BPU, prediction data can further include parameters of the loop filter (e.g., a loop filter strength).

[0079] FIG. 4 is a block diagram of an example apparatus 400 for encoding or decoding a video, consistent with embodiments of the disclosure. As shown in FIG. 4, apparatus 400 can include processor 402. When processor 402 executes instructions described herein, apparatus 400 can become a specialized machine for video encoding or decoding. Processor 402 can be any type of circuitry capable of manipulating or processing information. For example, processor 402 can include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), a neural processing unit (“NPU'), a microcontroller unit (“MCU’), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a

Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable

Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), or the like. In some embodiments, processor 402 can also be a set of processors grouped as a single logical component. For example, as shown in FIG. 4, processor 402 can include multiple processors, including processor 402a, processor 402b, and processor 402n.

[0080] Apparatus 400 can also include memory 404 configured to store data (e.g., a set of instructions, computer codes, intermediate data, or the like). For example, as shown in

FIG. 4, the stored data can include program instructions (e.g., program instructions for implementing the stages in processes 200 A, 200B, 300 A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). Processor 402 can access the program instructions and data for processing (e.g., via bus 410), and execute the program instructions to perform an operation or manipulation on the data for processing.

Memory 404 can include a high-speed random-access storage device or a non-volatile storage device. In some embodiments, memory 404 can include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or the like. Memory 404 can also be a group of memories

(not shown in FIG. 4) grouped as a single logical component.

[0081] Bus 410 can be a communication device that transfers data between components inside apparatus 400, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a universal serial bus port, a peripheral component interconnect express port), or the like.

[0082] For ease of explanation without causing ambiguity, processor 402 and other data processing circuits are collectively referred to as a “data processing circuit” in this disclosure. The data processing circuit can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. In addition, the data processing circuit can be a single independent module or can be combined entirely or partially into any other component of apparatus 400.

[0083] Apparatus 400 can further include network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communications network, or the like). In some embodiments, network interface 406 can include any combination of any number of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth adapter, an infrared adapter, an near-field communication (“NFC”) adapter, a cellular network chip, or the like.

[0084] In some embodiments, optionally, apparatus 400 can further include peripheral interface 408 to provide a connection to one or more peripheral devices. As shown in FIG. 4, the peripheral device can include, but is not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode-ray tube display, a liquid crystal display, or a light-emitting diode display), a video input device (e.g., a camera or an input interface coupled to a video archive), or the like.

[0085] It should be noted that video codecs (e.g., a codec performing process 200A,

200B, 300 A, or 300B) can be implemented as any combination of any software or hardware modules in apparatus 400. For example, some or all stages of process 200A, 200B, 300A, or

300B can be implemented as one or more software modules of apparatus 400, such as program instructions that can be loaded into memory 404. For another example, some or all stages of process 200 A, 200B, 300 A, or 300B can be implemented as one or more hardware modules of apparatus 400, such as a specialized data processing circuit (e.g., an FPGA, an

ASIC, an NPU, or the like).

[0086] In the quantization and inverse quantization functional blocks (e.g., quantization 214 and inverse quantization 218 of FIG. 2A or FIG. 2B, inverse quantization

218 of FIG. 3A or FIG. 3B), a quantization parameter (QP) is used to determine the amount of quantization (and inverse quantization) applied to the prediction residuals. Initial QP values used for coding of a picture or slice may be signaled at the high level, for example, using init_qp_minus26 syntax element in the Picture Parameter Set (PPS) and using slice qp delta syntax element in the slice header. Further, the QP values may be adapted at the local level for each CU using delta QP values sent at the granularity of quantization groups. [0087] In VVC, a palette mode can be used in 4:4:4 color format. When the palette mode is enabled, a flag is transmitted at the CU level if the CU size is smaller than or equal to

64x64 indicating whether the palette mode is used.

[0088] FIG. 5 illustrates a schematic diagram of an exemplary block 500 coded in palette mode, according to some embodiments of the present disclosure. As shown in FIG. 5, if the palette mode is utilized to code the current CU (e.g., block 500), the sample values in each position (e.g., position 501, position 502, position 503, or position 504) in the CU are represented by a small set of representative color values. The set is referred to as a “palette” or “palette table” (e.g., palette 510). For sample positions with values close to the palette colors, the corresponding palette indices (e.g., index 0, index 1, index 2, or index 3) are signaled. According to some disclosed embodiments, a color value that is outside the palette table can be specified by signaling an escape index (e.g., index 4). Then, for all positions in the CU that uses the escape color index, the (quantized) color component values are signaled for each of these positions.

[0089] For coding the palette table, a predictor palette is maintained. The predictor palette is initialized to 0 (e.g., empty) at the beginning of each slice for non-wavefront case and at the beginning of each CTU row for wavefront case. FIG. 6 illustrates a schematic diagram of an exemplary process 600 for updating predictor palette after encoding a coding unit, according to some embodiments of the present disclosure. As shown in FIG. 6, for each entry in the predictor palette, a reuse flag is signaled to indicate whether it will be included in the current palette table of the current CU. The reuse flags are sent using run-length coding of zeros, after which the number of new palette entries and the component values for the new palette entries are signaled. After encoding the palette coded CU, the predictor palette is updated using the current palette table, and entries from the previous predictor palette that are not reused in the current palette table are added at the end of the new predictor palette until the maximum size allowed is reached.

[0090] In some embodiments, an escape flag is signaled for each CU to indicate if escape symbols are present in the current CU. If escape symbols are present, the palette table is augmented by one and the last index is assigned to be the escape symbol (e.g., index 4 as shown in FIG. 5).

[0091 ] Referring to FIG. 5, palette indices of samples in a CU form a palette index map. The index map is coded using horizontal or vertical traverse scans. The scan order is explicitly signaled in the bitstream using the syntax element “palette transpose flag.” The palette index map is coded using the index-run mode or the index-copy mode.

[0092] Consistent with the some disclosed embodiments, when a picture is encoded, it is partitioned into a sequence of coding tree units (CTUs) and multiple CTUs can form a tile, a slice, etc. The partitioning of a picture into slices, tiles, and CTUs are described as follows.

[0093] A picture can be divided into a sequence of CTUs. For a picture that has three sample arrays, a CTU includes an NxN block of luma samples together with two corresponding NxN blocks of chroma samples. FIG. 7 illustrates a schematic diagram of an example of partitioning a picture into multiple CTUs, according to some embodiments of the present disclosure.

[0094] In some embodiments, the maximum allowed size of the luma blocks in a

CTU can be set to be 128x 128 (although the maximum size of the luma transform blocks is

64x64) and the minimum allowed size of the luma blocks in a CTU can be set to be 32x32.

[0095] A picture can be divided into one or more tile rows and one or more tile columns. A tile is a sequence of CTUs that covers a rectangular region of a picture. [0096] A slice includes an integer number of complete tiles or an integer number of consecutive complete CTU rows within a tile of a picture.

[0097] According to some embodiments, two modes of slices are supported: the raster-scan slice mode and the rectangular slice mode. In the raster-scan slice mode, a slice contains a sequence of complete tiles in a tile raster scan of a picture. In the rectangular slice mode, a slice can contain a number of complete tiles that collectively form a rectangular region of the picture or a number of consecutive complete CTU rows of one tile that collectively form a rectangular region of the picture. Tiles within a rectangular slice are scanned in tile raster scan order within the rectangular region corresponding to that slice.

[0098] FIG. 8 shows an example of partitioning a picture in the raster-scan slice mode, where the picture is divided into 12 tiles (4 tile rows and 3 tile columns) and 3 raster- scan slices, according to some embodiments of the present disclosure.

[0099] FIG. 9 shows an example of partitioning a picture in the rectangular slice mode, where the picture is divided into 20 tiles (5 tile columns and 4 tile rows) and 9 rectangular slices, according to some embodiments of the present disclosure.

[00100] FIG. 10 shows an example of a picture partitioned into tiles and rectangular slices, where the picture is divided into 4 tiles (2 tile columns and 2 tile rows) and 4 rectangular slices, according to some embodiments of the present disclosure.

[00101] As described above, the predictor palette is initialized to 0 (e.g., empty) at the beginning of a slice or at the beginning of a CTU row. In some embodiments, the predictor palette size is reset to 0 in one of the following three cases: (a) when the CTU is the first CTU in a slice, (b) when the CTU is the first CTU in a tile, and (c) when the value of syntax element entropy coding sync enabled flag is equal to 1 and the CTU is the first CTU in a

CTU row of a tile. [00102] When a picture is partitioned into multiple slice or tiles, or when wavefront parallel processing (WPP) is utilized to speed up the encoding and decoding processes, frequently resetting the predictor palette size may lead to a reduction of coding performance.

Thus, in some embodiments, to improve the coding performance, instead of resetting the predictor palette size to 0, a global predictor palette is used to initialize the predictor palette.

[00103] For example, a predictor palette initializer (e.g., a global predictor palette) is included in HEVC screen content extension. However, the design of HEVC predictor palette initializer cannot be directly applied to VVC draft 7. In VVC draft 7’s coding of an intra slice, the coding tree structures for luma samples and chroma samples of the CTU can be different (referred as dual-tree structure). In other words, the chroma samples of a CTU may have an independent coding tree block structure from the collocated luma samples in the same CTU. In VVC draft 7, in addition to the joint palette for single-tree structure, two new types of palette are included for dual-tree I slice, one having only luma components and the other having two chroma components. Moreover, in HEVC screen content extension, the predictor palette initializer is signaled in picture parameter set (PPS). In VVC draft 7, the predictor palette initializer may be signaled in the newly adopted high level syntax structure such as adaption parameter set (APS), picture header (PH), etc.

[00104] The present disclosure provides methods and apparatuses for implementing a

VVC-complied predictor palette initializer. As illustrated in the exemplary embodiments described below, the predictor palette initializer can be used to initialize the predictor palette, when a CTU meets one of the triggering conditions described above: (a) when the CTU is the first CTU in a slice, (b) when the CTU is the first CTU in a tile, and (c) when the value of syntax element entropy coding sync enabled flag is equal to 1 and the CTU is the first CTU in a CTU row of a tile. In some embodiments, the use of the VVC-complied predictor palette initializer can improve the coding performance. [00105] According to some embodiments, when the SPS syntax element qtbtt dual tree intra flag is set to 1, each CTU in an I slice is split into coding units with

64x64 luma samples using an implicit quadtree split and the resulted coding units are the root of two separate coding tree syntax structures for the luma and chroma components of the

CTU. The palettes for dual-tree I slice are separately used for the luma and chroma components. When syntax element qtbtt dual tree intra flag is set to 0, separate coding tree structures are not used and the palette for this mode is jointly used for the luma and chroma components. Because I slice uses separate luma and chroma palettes only when syntax element qtbtt dual tree intra flag is set to 1, a picture can use either joint palette or separate palette.

[00106] Consistent with the present disclosure, the predictor palette initializer can be defined based on whether joint or separate coding tree structures are used. The following description provides some embodiments (including syntax and semantics) for defining a predictor palette initializer.

[00107] FIG. 11 illustrates an exemplary Table 1 showing an exemplary predictor palette initializer syntax structure, according to some embodiments of the present disclosure.

As used in Table 1: joint predictor palette flag specifies if joint predictor palette or separate predictor palettes are signaled in the preidctor_palette_initializer structure. chroma_predictor_palette_present_flag specifies if chroma predictor palette is present. lumajpredictorjpalette_present_flag specifies if a luma predictor palette is present. Syntax element luma_predictor_palette_present_flag is only signaled when chroma_predictor_palette_present flag is equal to 1. When chroma_predictor_palette_present_flag is 0, then syntax element luma_predictor_palette_present flag is not signaled and its value is inferred to be 1. num_predictor_palette_entries_minus1, num_luma_predictor_palette_entries_minus1, and num_chroma_predictor_palette_entries_minus1 specify the numbers of “predictor palette entries-1” for joint, luma and chroma palettes, respectively. Their values are in a range of [0, PaletteMaxPredictorSize], where PaletteMaxPredictorSize is 63, according to some embodiments. predictor_palette_entry[comp][i] is the i-th predictor palette entry of a component “comp.” The bit depth of predictor_palette_entry is specified by the variable BitDepth, which is derived according to:

BitDepth = 8 + bit depth minus8, where bit depth minus8 is signaled in the SPS.

[00108] FIG. 12 illustrates an exemplary Table 2 showing another exemplary predictor palette initializer syntax structure, according to some embodiments of the present disclosure. As shown in Table 2, some differences from the syntax in Table 1 are shown in boxes 1201-1203 and highlighted in italics. As used in Table 2: joint_predictor_palette_present_flag equal to 1 specifies that a joint predictor palette syntax structure is present. Syntax element joint_predictor_palette_present_flag equal to 0 indicates that the joint predictor palette syntax structure is not present. separate_predictor_palette_present_flag equal to 1 specifies that a separate predictor palette syntax structure is present. Syntax element separate_predictor_palette_present_flag equal to 0 inidcates that the separate predictor palette syntax structure is not present. Syntax element separate_predictor_palette_present_flag is only signaled when syntax element joint_predictor_palette_present_flag is 1. When syntax element joint_predictor_palette_present_flag is 0, then syntax element separate_predictor_palette_present_flag is not signaled and its value is inferred to be

1.

[00109] Currently, palette mode is only allowed for 4:4:4 color format in VVC draft

7. In the 4:4:4 color format, a slice is either a dual-tree slice or a single-tree slice. However, in non 4:4:4 color format, such as 4:2:0 and 4:2:2 color formats, a coding unit (CU) of a single-tree slice can have separate luma and chroma trees due to the restriction on the smallest allowable chroma coding block sizes. Thus, different CUs in one slice may use joint palette or separate palette. The embodiments consistent with Table 2 allow both joint predictor palette and sepatate predictor palettes to be signaled in one predictor palette initializer syntax structure.

[00110] FIG. 13 illustrates an exemplary Table 3 showing another exemplary predictor palette initializer syntax structure, according to some embodiments of the present disclosure. As shown in Table 3, some differences from the syntax in Table 1 are shown in boxes 1301-1305 and highlighted in italics. As used in Table 3:

Iuma_bit_depth_entry_minus8 + 8 is the luma bit depth for predictor palette entries, and chroma_bit_depth_entry_minus8 + 8 is the chroma bit depth for the predictor palette entries. By explicitly signaling the predictor palette entry bit depth in APS syntax structure, the predictor palette entry may use a lower bit depth than the bit depth signaled in SPS.

[00111] Consistent with the disclosed embodiments, the predictor palette initializer described above in connection with Tables 1-3 may be signaled in the following raw byte sequence payloads (RBSP): sequence parameter set (SPS), picture parameter set (PPS), adaptation parameter set (APS), or picture header (PH).

[00112] According to some embodiments, the predictor palette initializer can be signaled in SPS or PPS. The picture referring to the SPS or PPS may use the predictor palette initializer for CTU initialization in the above-described the triggering conditions: (a) when the CTU is the first CTU in a slice, (b) when the CTU is the first CTU in a tile, and (c) when the value of syntax element entropy coding sync enabled flag is equal to 1 and the CTU is the first CTU in a CTU row of a tile.

[00113] According to some embodiments, the predictor palette initializer is signaled in APS. An APS type (PLT APS) can be dedicatedly assigned to predictor palette initializer

APS. FIG. 14 illustrates an exemplary Table 4 showing an exemplary APS syntax structure for signaling predictor palette initializer, according to some embodiments of the present disclosure. As shown in Table 4, the part of the APS syntax related to the predictor palette initializer is shown in box 1401 and highlighted in italics.

[00114] FIG. 15 illustrates an exemplary Table 5 showing an exemplary PH syntax structure for referencing to predictor palette initializer in APS, according to some embodiments of the present disclosure. As shown in Table 5, the proposed modification to the VVC draft 7’s PH syntax is shown in box 1501 and highlighted in italics. As shown in

Table 5: predictor_palette_initializer_present_flag specifies if predictor palette initializer is present. This flag is only signaled when syntax element sps_palette_enabled flag is 1. predictor_palette_aps_id specifies the APS identity (ID) of the predictor palette to which the picture header refers. [00115] FIG. 16 illustrates an exemplary Table 6 showing an exemplary picture header syntax structure for signaling predictor palette initializer, according to some embodiments of the present disclosure. As shown in Table 6, the proposed modification to the VVC draft 7’s PH syntax is shown in box 1601 and highlighted in italics. As used in

Table 6, predictor_palette_initializer_present_flag specifies if predictor palette initialized is present. This flag is only signaled when syntax element sps_palette_enabled_flag is 1.

[00116] Consistent with the disclosed embodiments, the above-described predictor palette initializer can be used to reset a predictor palette, when a CTU meets one of the triggering conditions described above: (a) when the CTU is the first CTU in a slice, (b) when the CTU is the first CTU in a tile, and (c) when the value of syntax element entropy coding sync enabled flag is equal to 1 and the CTU is the first CTU in a CTU row of a tile.

[00117] FIG. 17 illustrates an exemplary Table 7 showing an exemplary predictor palette initialization process (emphases shown in box 1701 and highlighted in italics), according to some embodiments of the present disclosure. Table 7 uses the predictor palette initializers defined in Table 1 and Table 2, consistent with some disclosed embodiments.

[00118] FIG. 18 illustrates an exemplary Table 8 showing another exemplary predictor palette initialization process (emphases shown in boxes 1801-1802 and highlighted in italics), according to some embodiments of the present disclosure. Table 8 uses the predictor palette initializer defined in Table 1, consistent with some disclosed embodiments.

[00119] It is a requirement of bitstream conformance that the value of syntax element

PredictorPaletteSize[ startComp ] is in the range of 0 to 63, inclusive.

[00120] FIG. 19 illustrates a flowchart of an exemplary palette coding method 1900, according to some embodiments of the present disclosure. Method 1900 can be performed by an encoder (e.g., by process 200A of FIG. 2A or 200B of FIG. 2B), a decoder (e.g., by process 300 A of FIG. 3A or 300B of FIG. 3B) or performed by one or more software or hardware components of an apparatus (e.g., apparatus 400 of FIG. 4). For example, a processor (e.g., processor 402 of FIG. 4) can perform method 1900. In some embodiments, method 1900 can be implemented by a computer program product, embodied in a computer- readable medium, including computer-executable instructions, such as program code, executed by computers (e.g., apparatus 400 of FIG. 4).

[00121] At step 1901, a predictor palette initializer signaled in a video bitstream can be accessed. For example, the predictor palette initializer can be the predictor palette initializer as shown in Table 2 of FIG. 12 or Table 3 of FIG. 13. In some embodiments, the predictor palette initializer can be accessed from an APS signaled in the video bitstream. A determination can be made on whether to access the predictor palette initializer from the APS based on a type of the APS. For example, as shown in box 1401 of Table 4 of FIG. 14, the predictor palette initializer can be accessed from the APS based on a syntax element aps_params_type. In some embodiments, method 1900 can include: determining, based on a picture header, an ID (e.g., syntax element predictor_palette_aps_id in Table 5 of FIG. 15) of the APS, and accessing the APS based on the ID (e.g. as shown in Table 5 of FIG. 15). In some embodiments, method 1900 can include accessing the predictor palette initializer from a PH (e.g. the PH as shown in Table 6 of FIG. 16) signaled in the video bitstream.

[00122] At step 1903, method 1900 can include determining that a first initial predictor palette is signaled in the predictor palette initializer based on a first flag in the predictor palette initializer. For example, the first flag can be syntax element j oint _j predi ctor_palette_present_flag as shown in Table 2 of FIG. 12 or Table 3 of FIG. 13.

The first initial predictor palette can be a joint predictor palette for coding luma components and chroma components of a CTU. [00123] At step 1905, method 1900 can include in response to the predictor palette initializer comprising a second flag, determining that a second initial predictor palette and a third initial predictor palette are signaled in the predictor palette initializer based on the second flag. For example, the second flag can be syntax element separate_predictor_palette_present_flag as shown in Table 2 of FIG. 12 or Table 3 of FIG.

13. In some embodiments, in response to the predictor palette initializer not comprising the second flag, method 1900 can include determining that the second initial predictor palette and the third initial predictor palette are signaled in the predictor palette initializer. The second flag can be inferred to be 1. In some embodiments, a determination can be made on whether the second flag is signaled in the predictor palette initializer based on the first flag (e.g., as shown in Table 2 of FIG. 12 or Table 3 of FIG. 13).

[00124] In some embodiments, method 1900 can include: determining whether the second initial predictor palette is signaled in the predictor palette initializer based on a third flag, or determining whether the third initial predictor palette is signaled in the predictor palette initializer based on a fourth flag. The second initial predictor palette can be used for coding luma components of the CTU, and the third initial predictor palette can be used for coding chroma components of the CTU. The third flag can be syntax element

1 um a_predictor_pal ette_present fl ag, and the fourth flag can be syntax element chroma_predictor_palette_present_flag, shown in Table 2 of FIG. 12 or Table 3 of FIG. 13.

[00125] In some embodiments, method 1900 can include: determining whether a bit depth for predictor palette entries of the first initial predictor palette based on the first flag, or determining whether a bit depth for predictor palette entries of the second or third initial predictor palette based on the second flag. For example, as shown in boxes 1301, 1304, and

1305 of Table 3 of FIG. 13, the bit depth for predictor palette entries can be syntax element luma_bit_depth_entry_minus8 or chroma_bit_depth_entry_minus8. [00126] In some embodiments, method 1900 can include: determining whether a condition for triggering predictor palette initialization is met; and in response to a determination that the condition is met, setting a predictor palette for a coding unit based on the predictor palette initializer (e.g. the predictor palette initialization process as shown in

Table 7 of FIG. 17 or Table 8 of FIG. 18).

[00127] The embodiments may further be described using the following clauses:

1. A palette coding method, comprising: determining, based on a first flag, whether a first initial predictor palette is signaled in a predictor palette initializer; and in response to the first initial predictor palette being signaled in the predictor palette initializer, determining, based on a second flag, whether a second initial predictor palette and a third initial predictor palette are signaled in the predictor palette initializer.

2. The method of clause 1, wherein in response to the first initial predictor palette being signaled in the predictor palette initializer, determining, based on the second flag, whether the second initial predictor palette and the third initial predictor palette are signaled in the predictor palette initializer comprises: in response to that the second flag is not signaled in the predictor palette initializer, determining that the second initial predictor palette and the third initial predictor palette are signaled in the predictor palette initializer.

3. The method of any one of clauses 1 and 2, further comprising: determining, based on the first flag, whether the second flag is signaled in the predictor palette initializer. 4. The method of any one of clauses 1-3, further comprising: determining, based on a third flag, whether the second initial predictor palette is signaled in the predictor palette initializer; or determining, based on a fourth flag, whether the third initial predictor palette is signaled in the predictor palette initializer.

5. The method of any one of clauses 1-4, further comprising: in response to the first initial predictor palette being signaled in the predictor palette initializer, determining a bit depth for predictor palette entries of the first initial predictor palette.

6. The method of any one of clauses 1 -5, further comprising: in response to the second initial predictor palette and the third initial predictor palette being signaled in the predictor palette initializer, determining a bit depth for predictor palette entries of the second or third initial predictor palette.

7. The method of any one of clauses 1-6, wherein the first initial predictor palette is a joint predictor palette for coding luma components and chroma components of a coding tree unit (CTU).

8. The method of any one of clauses 1-7, wherein the second initial predictor palette is used for coding luma components of the CTU, and the third initial predictor palette is used for coding chroma components of the CTU.

9. The method of any one of clauses 1-8, further comprising: accessing the predictor palette initializer from an adaption parameter set (APS).

10. The method of clause 9, further comprising: determining, based on a type of the APS, whether to access the predictor palette initializer from the APS.

11. The method of clause 9, further comprising: determining, based on a picture header, an identity (ID) of the APS; and accessing the APS based on the ID.

12. The method of any one of clauses 1-11, further comprising: accessing the predictor palette initializer from a picture header (PH).

13. The method of any one of clauses 1-12, further comprising: determining whether a condition for triggering predictor palette initialization is met; and in response to a determination that the condition is met, setting a predictor palette for a coding unit based on the predictor palette initializer.

14. A video processing apparatus, comprising: at least one memory for storing instructions; and at least one processor configured to execute the instructions to cause the apparatus to perform: determining, based on a first flag, whether a first initial predictor palette is signaled in a predictor palette initializer; and in response to the first initial predictor palette being signaled in the predictor palette initializer, determining, based on a second flag, whether a second initial predictor palette and a third initial predictor palette are signaled in the predictor palette initializer.

15. The apparatus of clause 14, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: in response to that the first initial predictor palette is signaled in the predictor palette initializer and the second flag is not signaled in the predictor palette initializer, determining that the second initial predictor palette and the third initial predictor palette are signaled in the predictor palette initializer.

16. The apparatus of any one of clauses 14 and 15, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: determining, based on the first flag, whether the second flag is signaled in the predictor palette initializer.

17. The apparatus of any one of clauses 14-16, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: determining, based on a third flag, whether the second initial predictor palette is signaled in the predictor palette initializer; or determining, based on a fourth flag, whether the third initial predictor palette is signaled in the predictor palette. 18. The apparatus of any one of clauses 14-17, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: in response to the first initial predictor palette being signaled in the predictor palette initializer, determining a bit depth for predictor palette entries of the first initial predictor palette.

19. The apparatus of any one of clauses 14-18, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: in response to the second initial predictor palette and the third initial predictor palette being signaled in the predictor palette initializer, determining a bit depth for predictor palette entries of the second or third initial predictor palette.

20. The apparatus of any one of clauses 14-19, wherein the first initial predictor palette is a joint predictor palette for coding luma components and chroma components of a coding tree unit (CTU).

21. The apparatus of any one of clauses 14-20, wherein the second initial predictor palette is used for coding luma components of the CTU, and the third initial predictor palette is used for coding chroma components of the CTU.

22. The apparatus of any one of clauses 14-21, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: accessing the predictor palette initializer from an adaption parameter set (APS). 23. The apparatus of clause 22, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: determining, based on a type of the APS, whether to access the predictor palette initializer from the APS.

24. The apparatus of clause 22, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: determining, based on a picture header, an identity (ID) of the APS; and accessing the APS based on the ID.

25. The apparatus of any one of clauses 14-24, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: accessing the predictor palette initializer from a picture header (PH).

26. The apparatus of any one of clauses 14-25, wherein the at least one processor is configured to execute the instructions to cause the apparatus to perform: determining whether a condition for triggering predictor palette initialization is met; and in response to a determination that the condition is met, setting a predictor palette for a coding unit based on the predictor palette initializer.

27. A non-transitory computer readable storage medium storing a set of instructions that are executable by one or more processing devices to cause a video processing apparatus to perform a method comprising: determining, based on a first flag, whether a first initial predictor palette is signaled in a predictor palette initializer; and in response to the first initial predictor palette being signaled in the predictor palette initializer, determining, based on a second flag, whether a second initial predictor palette and a third initial predictor palette are signaled in the predictor palette initializer.

28. The non-transitory computer readable storage medium of clause 27, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: in response to that the first initial predictor palette is signaled in the predictor palette initializer and the second flag is not signaled in the predictor palette initializer, determining that the second initial predictor palette and the third initial predictor palette are signaled in the predictor palette initializer.

29. The non-transitory computer readable storage medium of any one of clauses 27 and 28, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: determining, based on the first flag, whether the second flag is signaled in the predictor palette initializer.

30. The non-transitory computer readable storage medium of any one of clauses 27-

29, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: determining, based on a third flag, whether the second initial predictor palette is signaled in the predictor palette initializer; or determining, based on a fourth flag, whether the third initial predictor palette is signaled in the predictor palette.

31. The non-transitory computer readable storage medium of any one of clauses 27-

30, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: in response to the first initial predictor palette being signaled in the predictor palette initializer, determining a bit depth for predictor palette entries of the first initial predictor palette.

32. The non-transitory computer readable storage medium of any one of clauses 27-

31 , wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: in response to the second initial predictor palette and the third initial predictor palette being signaled in the predictor palette initializer, determining a bit depth for predictor palette entries of the second or third initial predictor palette.

33. The non-transitory computer readable storage medium of any one of clauses 27-

32, wherein the first initial predictor palette is a joint predictor palette for coding luma components and chroma components of a coding tree unit (CTU).

34. The non-transitory computer readable storage medium of any one of clauses 27-

33, wherein the second initial predictor palette is used for coding luma components of the

CTU, and the third initial predictor palette is used for coding chroma components of the

CTU. 35. The non-transitory computer readable storage medium of any one of clauses 27-

34, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: accessing the predictor palette initializer from an adaption parameter set (APS).

36. The non-transitory computer readable storage medium of clause 35, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: determining, based on a type of the APS, whether to access the predictor palette initializer from the APS.

37. The non-transitory computer readable storage medium of clause 35, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: determining, based on a picture header, an identity (ID) of the APS; and accessing the APS based on the ID.

38. The non-transitory computer readable storage medium of any one of clauses 27-

37, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: accessing the predictor palette initializer from a picture header (PH). 39. The non-transitory computer readable storage medium of any one of clauses 27-

38, wherein the set of instructions are executable by the one or more processing devices to cause the video processing apparatus to perform: determining whether a condition for triggering predictor palette initialization is met; and in response to a determination that the condition is met, setting a predictor palette for a coding unit based on the predictor palette initializer.

[00128] In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and the instructions may be executed by a device

(such as the disclosed encoder and decoder), for performing the above-described methods.

Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a CD-

ROM, any other optical data storage medium, any physical medium with patterns of holes, a

RAM, a PROM, and EPROM, a FLASH-EPROM or any other flash memory, NVRAM, a cache, a register, any other memory chip or cartridge, and networked versions of the same.

The device may include one or more processors (CPUs), an input/output interface, a network interface, and/or a memory.

[00129] It should be noted that, the relational terms herein such as “first” and

“second” are used only to differentiate an entity or operation from another entity or operation, and do not require or imply any actual relationship or sequence between these entities or operations. Moreover, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items. [00130] As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[00131] It is appreciated that the above described embodiments can be implemented by hardware, or software (program codes), or a combination of hardware and software. If implemented by software, it may be stored in the above-described computer-readable media.

The software, when executed by the processor can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, or software, or a combination of hardware and software. One of ordinary skill in the art will also understand that multiple ones of the above described modules/units may be combined as one module/unit, and each of the above described modules/units may be further divided into a plurality of sub-modules/sub-units.

[00132] In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation.

Certain adaptations and modifications of the described embodiments can be made. Other embodiments can be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. It is also intended that the sequence of steps shown in figures are only for illustrative purposes and are not intended to be limited to any particular sequence of steps. As such, those skilled in the art can appreciate that these steps can be performed in a different order while implementing the same method. [00133] In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.