The invention relates to vestigial sideband (VSB) signal receivers and, more particularly, the invention relates to timing recovery circuits for such VSB receivers.

BACKGROUND OF THE DISCLOSURE A conventional vestigial sideband (VSB) signal receiver for a high definition television (HDTV), as described in the"Guide To The Use Of The ATSC Digital Television Standard"Document A/54, Advanced Television Systems Committee, pp. 110-111, April 12,1995 which is incorporated herein in its entirety by reference, contains an analog circuit to perform carrier recovery.

The conventional carrier recovery process uses a frequency locked loop (FLL) and a phase lock loop (PLL) that cooperatively operate to lock onto a pilot carrier of the VSB signal. The recovered carrier signal is then used to produce the in- phase and quadrature components of the VSB signal. Once the VSB signal components are recovered, the in-phase (I) component is digitized and then digitally processed to recover symbol timing and decode the data transmitted within the VSB signal.

Symbol timing recovery is performed using the digitized I component only.

To accomplish accurate timing recovery using only the I component, the timing recovery circuitry of the VSB signal receiver must detect a four symbol segment synchronization header within the data of the VSB signal. The synchronization header is used to synchronize the receiver symbol timing with the received signal such that the symbols can be accurately decoded to recover the data transmitted within the VSB signal. Consequently, current VSB receivers must have analog circuitry to perform certain functions prior to digitization of the

signal and must utilize synchronization header information to achieve accurate symbol timing. The use of analog circuitry is prone to add noise to the received signal and the processing required for decoding the synchronization header is an inefficient use of the receiver.

Therefore, there is a need in the art for a digital passband carrier and timing recovery circuit that performs carrier recovery and symbol timing recovery upon a VSB signal to recover the in-phase and quadrature-phase components of the VSB signal.

SUMMARY OF THE INVENTION The disadvantages associated with the prior art are overcome by the invention of a method and apparatus for performing phase detection and timing recovery for a vestigial sideband (VSB) signal by processing a complex valued passband VSB signal using a high order non-linearity to detect the phase of the VSB signal. The non-linearity is produced by extracting the complex bandedge signals from a VSB signal and multiplying the complex conjugate of the lower bandedge signal with the upper bandedge signal using a complex multiplier.

The real and imaginary components of the output of the complex multiplier are then multiplied with one another using a real multiplier. The result is a phase error signal that is used as a control signal for a numerically controlled oscillator. The non-linearity can be mathematically defined as: v (t) = g+ (t) x g (t) y (t) = sgn (Re {v (t)}) x Im {v (t)} where y (t) is the is the output (phase error signal) of the phase detector, g, (t) is the complex upper (positive frequency) bandedge signal, g.' (t) is the complex conjugate of the lower (negative frequency) bandedge signal. As such, an all digital solution to timing recovery from a VSB signal for a high definition television is provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a simplified block diagram of a vestigial sideband (VSB) signal receiver incorporating the present invention; FIG. 2 is a detailed block diagram of a carrier and timing recovery circuit in accordance with the present invention; FIG. 3 is a detailed diagram of the phase detector of the present invention; and FIG. 4 is a block diagram of an NCO used in the carrier and timing recovery circuit of FIG. 2.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

DETAILED DESCRIPTION FIG. 1 is a simplified, block diagram of a vestigial sideband (VSB) signal receiver 100 for a high definition television (HDTV) containing a tuner 104, an analog-to-digital (A/D) converter 106, a free-running oscillator 108, a timing recovery circuit 110, and a decoder 112. Input connector 102 is generally connected to a source of the VSB signal such as a cable television network or an antenna. The tuner 104 selects a particular channel from a plurality of channels to couple a particular VSB signal to the analog-to-digital converter 106. The A/D converter 106 digitizes the selected VSB signal. The sample frequency generated by the free-running oscillator 108 is at least two times the symbol rate of the VSB signal. The digitized signal has a nominal frequency of one-fourth the sampling rate (fp/4) and is coupled to the carrier and timing recovery circuit 110 to synchronize the symbol sampling process of the receiver to the received VSB signal. The carrier and timing recovery circuit 110 is an all digital circuit that extracts the in-phase (I) and quadrature phase (Q) signals from the digitized VSB signal. The I and Q signals are coupled to the decoder 112 which extracts data from the I component of the received signal.

FIG. 2 depicts a detailed block diagram of the timing recovery circuit 110 of FIG. 1. The timing recovery circuit 110 contains a frequency shifter 200, a decimation filter 201, a polyphase interpolation filter 202, a bandedge prefilter 204, a phase detector 206, a loop filter 208 and a sampling numerically controlled oscillator (NCO) 210. The bold connective paths of FIG. 2 represent complex signal paths and the non-bold connective paths represent real signal paths.

The timing recovery circuit 110 operates using a single clock. However, the circuit 110 operates at three processing rates, i. e., the sampling rate (fSamp), half the sampling rate (5ami/2) and the symbol rate (fSym) To achieve these three processing rates with a single clock, the various subcircuits are selectively enabled to perform synchronous processing on desired cycles.

The frequency shifter operates by multiplying the digitized VSB signal (a <BR> <BR> <BR> <BR> in<BR> <BR> <BR> <BR> <BR> real signal) with samples of a complex sinusoid x (n) = e''' (having a frequency of one-fourth the sampling rate). To correctly shift the frequency to enable the invention to function, the sampling rate is chosen such that the aliased copies of the VSB signal are located at 1/4 the sampling frequency. For example, the IF frequency of the signal generated by the tuner is nominally 43.75 MHz and that signal is subsampled at 25 MHz resulting in signal aliases at 6.25 MHz. Since the values of x (n) are always in the set {1, j,-1, j), the frequency shift operation shifts the digitized signal to DC and is performed with only multiplexers and inverters, thus keeping the circuit rather simple and inexpensive to implement.

The output of the frequency shifter 200 is a passband signal that is shifted to DC and contains complex in-phase (I) and quadrature phase (Q) components of the VSB signal having upper and lower bandedges at f/4. The decimation filter 201 removes undesired sidebands and spectral aliases from the frequency shifted signal, and provides a sampling rate reduction for the interpolation filter 202.

The decimation filter 201 is an N-tap low pass FIR filter having real valued coefficients. After filtering, every other output sample is discarded such that the output rate is Samp/2 (e. g., 12.5 MHz). An illustrative filter is a symmetric, odd- length, windowed-sinc function having all non-zero even filter coefficients and only one non-zero odd coefficient at the center of the filter. With the tap coefficients being symmetric about (N-1)/2, the decimation filter is defined by the followingequation:

where T'=2T and T is the symbol period as well as the tap spacing; n is the sample index of the filter output; k is a sample index used for the convolutional sum; and h () are the samples of a sinc function.

This filter is efficiently implemented using only ( multiplication functions. If the filter is clocked at twice the sampling frequency, then the actual number of hardware multipliers can be reduced by a factor of four by using resource sharing. For example, a 23-tap, complex decimation filter (having 13 non-zero, real valued coefficients) requires 7 multiply operations and, with resource sharing, can therefore be implemented using only 2 hardware multipliers.

The polyphase interpolation filter 202 removes any undesired spectrum from the decimated VSB signal (i. e., high frequency components are suppressed) and adds a timing delay specified by the output (a phase selection signal) of the numerically controlled oscillator (NCO) 210. The polyphase filter is implemented using a conventional polyphase FIR lowpass filter having a pulse shape with zero amplitude at multiples of the symbol period. By proper variation of the phase selection signal, the NCO can drive the polyphase interpolation filter to perform sampling rate conversion. Specifically, the NCO 210 accumulates values of phase error presented at its input and uses the accumulated value to drive the phase selection port of the polyphase filter 202.

The input to the NCO 210 controls the rate of accumulation and, therefore, the rate at which the phase select signal changes. When producing a phase select signal having the form of a linear ramp, the polyphase interpolation filter

performs a sampling rate conversion. The input rate to the interpolation filter is Fs p/2 (12.5 MHz) which is faster than the symbol rate 5, m (10.76 MHz). The filter is implemented to have 256 selectable phases using a Hamming-windowed sinc function. The interpolation filter generates output data at a rate of fs, p/4, with a desired output data rate of fsym To obtain this rate, the sampling NCO controls the phase selection of the interpolation filter and generates an enable signal for the bandedge prefilter 204 to control data flow from the interpolation filter 202. The phase select signal and the enable signal change at an average rate of fsw, thus performing the desired rate conversion. After convergence of the carrier and timing recovery loop, the input to the NCO 210 will (roughly) become a constant value and the output rate of the interpolation filter 202 is the symbol rate The output signal of the polyphase interpolation filter 202 is a resampled passband VSB signal, containing complex I and Q components.

The bandedge prefilter 204 extracts bandedge information from the resampled VSB signal by performing a positive and a negative frequency shift (using frequency shifters 204A and 204B) on the output of the interpolation filter 202 and then lowpass filters (filters 204C and 204D) the frequency shifted results. The frequency shift is performed in blocks 204A and 204B by ; 7t multiplying the complex input signal with a complex sinusoid x (n) = e One frequency shifter 204A and 204B is required for each bandedge. As such, shifter 204A shifts the complex input signal by-f"",/4 and shifter 204B shifts the complex input signal bv +5, =,/4. Since the values of x (n) are always in the set {i, j,-1, j), the frequency shifting operation can be performed with only multiplexers and inverters, thus keeping the circuit rather simple and inexpensive to implement.

The lowpass filter portions of the prefilter 204 can be implemented using a pair of single pole lowpass IIR filters 204C and 204D. If the pole of each filter 204C and 204D is constrained to lie at z = (2N-1)/2N, where N is an integer value greater than 0, the lowpass filter can be implemented using simple shifters and adders.

Generally, a second-order nonlinearity that is typically used for QAM signal timing recovery is insufficient for VSB signals. Consequently, the carrier and timing recovery circuit of the present invention uses a unique, higher order nonlinearity mathematically defined by: v (t) = g+ (t) x g= (t) y(t) = sgn (Re {v (t)}) x Im {v (t)} where y (tj is the is the output of the phase detector, g, (t) is the complex valued prefilter output for the upper (positive frequency) bandedge, g (t) is the complex conjugate of the prefilter output for the lower (negative frequency) bandedge.

The output v (t) has been proposed for phase detection in QAM systems in Godard."Passband Timing Recovery in an All-Digital Modem Receiver". IEEE Transactions on Communications, com-26. No. 5. May 1978. The additional processing to generate y (t) by multiplying the real and imaginary components of u (t) permits phase detection for VSB systems, i. e., the magnitude of the signal y (t) is proportional to the phase error of the received VSB signal with respect to the receiver clock.

FIG. 3 depicts a block diagram representation of the foregoing equation pair, where the lower bandedge signal g. (t) is processed in complex conjugate block 300. The complex conjugate of the lower bandedge signal gaz (t) is then applied to a first input of a complex multiplier 302. The second input of the multiplier is the upper bandedge signal g, (t) such that the output of the complex multiplier 302 is v (t). The signal v (t) is the applied to a imaginary component extractor 308 that applies only the imaginary component of the signal vft) to a first input of a real multiplier 310. The signal v (t) is also applied to a real component extractor 304 that extracts the real component of the signal v (t) and applies it to a signum (sgn) function block 306. The output of the signum function block 306 is applied to the second input of the real multiplier 310. The output of the multiplier 310 is the signal y (t), also referred to as the phase error signal.

Returning to FIG. 2, the output of the phase detector 206 is a real valued signal that is coupled to the loop filter 208. The loop filter 208 is a conventional, second order digital lowpass filter that facilitates frequency and phase tracking

by the timing recovery loop. The output of the loop filter is coupled to the control port of the NCO 210.

FIG. 4 depicts a simplified block diagram of the NCO 210. The NCO 210 contains an accumulator 400 and an overflow detector 402. For a constant control signal from the loop filter, the output phase select signal of the NCO 210 is a periodic signal at the Tsw rate, i. e., the appropriate resampling rate for the interpolation filter when the phase error is zero. The difference (an incremental time delay d) within the interpolation filter between the input sample locations that occur at a rate of TSSMP/2 and the output sample locations that occur at a rate ofT accumulates within the accumulator 400. To optimize the interpolation, it is desirable to maintain the output sample time (location) close to the input sample time (location). When the phase of the received VSB signal is changing with respect to the receiver clock, the time delay d will vary, i. e., will slew with phase error. Consequently, the difference between when an input sample occurs in time and when an output sample occurs in time will increase with the passing of each symbol period until the delay exceeds an entire period. The accumulator 400 adds the previous time delay to the next time delay, and the next time delay, and so on. This increasing accumulation forms the phase select signal, i. e., a linear ramp. When the delav detector 402 detects that the delay has accumulated to a value that exceeds the sampling period TSamp/2 the bandedge filter 204 is disabled for one sampling period to halt the phase detection process for one symbol period. This brings the sampling locations within the TS=p/2 and the Tspperiods near one another within a symbol period and restarts the time delay accumulation.

The carrier and timing recovery circuit of the present invention provides an all digital technique for performing timing recovery in a VSB signal receiver of an HDTV. By using the invention in lieu of the analog timing recovery circuits of the prior art, the circuitry of a receiver using the invention will be less prone to adding noise to the received signals and less expensive to implement.

Although the foregoing embodiments of the invention are described in the context of a hardware implementation, those skilled in the art will realize that the invention can be implemented, in whole, or in part, as a software routine

executing upon a general purpose computer. Such a software routine would be stored until executed upon a computer readable medium. The invention can also be implemented, in whole, or in part, as an application specific integrated circuit (ASIC). The description of particular techniques for implementing the invention should not be considered limiting the scope of the invention in any manner.

Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.