Title:
METHOD AND APPARATUS FOR PHYSICAL BUDGETING DURING RTL FLOORPLANNING
Document Type and Number:
WIPO Patent Application WO2002037343
Kind Code:
A8
Abstract:
A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget (FIGURE 1, step 3) includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan (FIGURE 1, step 5). Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block (FIGURE 1, step 8). The global constraints are allocated proportionally to each block based on the feasible timing for each block.
Inventors:
GINETTI ARNOLD
Application Number:
PCT/US2001/045441
Publication Date:
July 11, 2002
Filing Date:
October 30, 2001
Export Citation:
Assignee:
CADENCE DESIGN SYSTEMS INC (US)
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50
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