TECHNICAL FIELD

The present disclosure is related to timing recovery in systems with strong intersymbol interference.

In this context, the present disclosure refers to a method for timing recovery (TR) in faster- than-Nyquist n-level pulse amplitude modulation (FTN PAM-n) systems.

The present disclosure also refers to an apparatus for timing recovery (TR) in faster-than- Nyquist (FTN) n-level pulse amplitude modulation (FTN PAM-n) systems.

Furthermore, the present disclosure refers to a computer program comprising instructions which, when the program is executed by a computer, cause the computer to execute the steps of the method.

Furthermore, the present disclosure refers to a computer-readable medium comprising instructions which, when executed by a computer, cause the computer to execute the steps of the method.

BACKGROUND

According to prior art methods, optical transceivers used for data centers use very cheap components such as directly modulated lasers (DML) and electro absorption modulators (EML). The power of optical signal is almost proportional to the electrical signal that modulates the laser. DSP consumption and latency are very critical and only basic DSP functions are implemented in commercial products. Forward-error correction (FEC) is necessary at higher data rates. These codes are often standardized but they can also be proprietary. After mapping bits into PAM levels, PAM signal can be pre-equalized to improve performance. A digital-to-analog converter (DAC) outputs an analog electrical signal that is often amplified by a modulator driver (MD). EML / DML output optical signal may suffer from chromatic dispersion (CD) in longer links. Therefore, in some systems dispersion compensation fibers (DCF) or dispersion compensation modules (DCM) are used to compensate for CD. At the receiver side, a photo detector/diode (PDet) detects the optical signal. The PDet output is proportional to the optical signal power. The PDet output is amplified by using a transimpedance amplifier (TIA). PDet and TIA can be integrated in receive optical subassemblies (ROSA) that may include an automatic gain control circuit (AGO) to adjust electrical signal to an analog-to-digital (ADC) input when electronic equalization is used. The receiver can use a feed-forward equalizer (FFE), a decision feed-back equalizer (DFE), a maximum likelihood sequence estimator (MLSE), or combine some of them at the receiver. FFEs suffer from noise enhancement, DFEs suffer from error multiplication, while MLSE represents a good and complex solution for both. At the end, hard FECs are normally used after the PAM demapper.

An AGO block monitors signal power variations and produces almost constant signal swing that fits into ADC input range. In this way the ADC is effectively used. An equalizer recovers signal suffering from noise and intersymbol interference (ISI). However, before the equalizer is activated the local oscillator is locked to the input signal, i.e. to the transmitter oscillator responsible for data clocking. These two oscillators are synchronized. Small phase deviations are allowed since it is impossible to perfectly track the transmitter clock phase. Clock extraction is enabled by a phase detector (PD) that outputs information whether sampling clock is faster or slower. Since this information is noisy suffering from pattern- dependent noise, noise caused by amplifiers, component imperfections, etc., timing information is filtered before entering/controlling the receiver oscillator, often realized as a voltage-controlled oscillator (VCO).

Timing information can be derived from ADC output signal. Timing recovery (TR) block includes PD, low-pass filter and VCO. VCO clock phase can be adjusted using a sampling phase adjustment (SPA) circuit. Sampling phase optimization can be also supported by an FEC decoder that provides a number of FEC input errors (number of corrected errors). A good sampling phase should minimize this number.

The transmitted signal x is modified by the system transfer function H that can be approximated by a linear system. In general, the system is nonlinear. The output signal is a convolution of the signal x and the system pulse response h where ISI spreads the input signal over 2n+1 symbol intervals. Usually, the transfer function behaves as a low-pass filter and high frequency components can be severely attenuated. An additive noise n additionally disturbs the signal x. The TR block gets a signal suffering from ISI and noise. TR designers count with noise and practical TR solutions are less sensitive to noise in the specified working conditions. For example, a pre-FEC bit error rate (BER) is directly related to the amount of noise that can be tolerated by the system. However, in systems using enhanced equalization techniques to cope with ISI caused by strong bandwidth limitations of optical and electrical components the received signal contains insufficient clock information. In such systems, many practical TR schemes fail because the frequency content around Nyquist frequency is very pure.

The receiver complexity is critical for data center applications. Therefore, the preferred ADC sampling rate is one sample per symbol (1sps). The 1sps sampling rate does not allow the implementation of TR interpolators after the ADC when a phase-locked loop (PLL) latency becomes critical because interpolators require more than 1sps sampling rate. The PLL latency introduces jitter peaking that causes problems during clock offset acquisition and jitter tracking. When clock quality is low the clock offset acquisition often fails with classical PDs. To solve this problem a phase-frequency detector (PFD) is required but this solution also requires more than 1sps sampling rate.

The conventional PFD implemented before ADC is often based on NAND D-flip-flop methods and the speed of flip flops limits the operating frequency and slows the frequency acquisition. This method can only work in systems with almost no ISI. However, it becomes impractical in FTN systems. Usually, PFDs are designed to be linear but linear and nonlinear ISI makes them instable and impractical. In some cases, they do not have the equilibrium point or a timing error detector characteristic (TEDC) is extremely irregular and asymmetrical. The nonlinear TEDC may cause very long clock offset acquisition.

A Gardner phase detector output is described by where T denotes symbol interval and t is the sampling phase. Let us denote this output by TEDCI (in-phase TEDC). The quadrature TEDC (TEDCQ) can be obtained by

TEDCQ{ t) = TEDCI (t + Q.

Both TEDCs have sinusoidal shape and they can be used in the PFD with output ATEDC = atan2(TEDCI, TEDCQ) followed by an unwrap block that makes TEDC fully linear over unlimited number of symbols. This PFD detector completely fails in FTN systems and there is no any TR filter that can improve its performance. This PFD relies on frequencies that are around the Nyquist frequency. In FTN systems, signal to noise ratio (SNR) at these frequencies is lower than 1 and the equalization does not provide a solution. In some cases, it can enable clock extraction but with a large self-jitter, unacceptable cycle slip probability, and low tolerance to deterministic jitter.

All these solutions require more than 1 sps sampling rate.

SUMMARY

In view of the above-mentioned problems and disadvantages, the present disclosure aims to improve the current implementations.

It is an object of the present disclosure to provide an improved method, an improved apparatus, an improved computer program, and an improved computer-readable medium. Preferably, TR in faster-than-Nyquist n-level pulse amplitude modulation (FTN PAM-n) systems should be provided, which allows appropriate phase-frequency detection in case that only 1 sps sampling rate is only available.

This object is achieved by the independent claims. Advantageous implementation forms are given in the dependent claims. The claimed subject matter is not limited to implementations that solve only the noted disadvantages.

According to an aspect of the disclosure, a method for timing recovery (TR) in faster-than- Nyquist n-level pulse amplitude modulation (FTN PAM-n) systems is provided. The method comprises steps of: receiving, by a receiver system, a signal; and for acquiring clock information from the signal, applying an arctan-function with one sample per symbol, sps, on the signal, by the receiver system.

According to another aspect of the disclosure, an apparatus for timing recovery (TR) in faster-than-Nyquist n-level pulse amplitude modulation (FTN PAM-n) systems is provided. The apparatus comprises a receiver system configured to: receive a signal; and for acquiring clock information from the signal, apply an arctan-function with one sample per symbol, sps, on the signal. Alternatively, or additionally, the apparatus comprises components adapted to carry out steps according to any of the preferred implementation forms.

Another aspect of the disclosure refers to a computer program comprising instructions which, when the program is executed by a computer, cause the computer to execute the steps of the method. A computer program is a collection of instructions for performing a specific task that is designed to solve a specific class of problems. The instructions of a program are designed to be executed by a computer and it is required that a computer can execute programs in order to it to function.

Another aspect of the disclosure refers to a computer-readable medium comprising instructions which, when executed by a computer, cause the computer to execute the steps of the method.

The disclosure refers to a method for clock derivation in PAM-n transmission systems that are seriously degraded by ISI caused by bandwidth limitations of electrical and optical components. The method has the advantages that the new phase frequency detector uses one sample per symbol that enables the clock extraction at very high baud rates with very low complexity and the TR architecture is very robust against the TR loop delay.

Optionally, TR is carried out in a phase frequency detector mode (PFD mode) and after having acquired the clock information, TR is carried out in a phase detector mode (PD mode). In other words, after clock offset acquisition, the TR is reconfigured to work in the PD mode. This allows that the TR loop delay is shortened and the TR complexity is minimized.

Optionally, before the step of applying the arctan-function, the method comprises a step of applying different timing recovery filters (TR filters) on the signal. The TR filters allow TR to lock. More specifically, they are configured such that they modify the timing error detector characteristic (TEDC) such that TR can lock.

Optionally, a TR filter applied in an in-phase mode differs from a TR filter applied in a quadrature mode. The different TR filters are applied to provide different TEDCs, for example.

Optionally, in the quadrature mode, the TR filter is applied for a phase shift of the signal. This allows that the TEDC, which is provided by the TR filter of the quadrature mode, is shifted compared to the TEDC provided by the TR filter in the in-phase mode.

Optionally, the TR filter is applied for the phase-shift by TT/2 (Pi/2). Optionally, the TR filter is applied for signal equalization. This is a simple and with small effort realizable possibility to provide signals with less distortion for further processing steps.

Optionally, the different TR filters are applied in the PFD mode. For example, this allows to provide PFD with small processing effort compared to PFD according to prior art.

Optionally, the method comprises, before the step of applying the arctan-function, a step of averaging signal outputs of the PD, by one or more infinite impulse response filters (MR filters).

Optionally, after the step of applying the arctan-function, the method comprises a step of unwrapping and a step of filtering TR estimations. Thereby, a continuous and smooth signal may be provided for subsequent processing steps.

Optionally, the TR filters comprise multiple timing recovery filter taps (TR filter taps) wherein the method comprises using a training sequence for providing each of the TR filter taps. The advantage is that quite a small number of TR filter taps is sufficient for providing an adequate TR filter. The training sequence may be selected in accordance with typical signal characteristics of signals for which TR is carried out.

Optionally, the training sequence is used during an autonegotiation. Autonegotiation refers to a method that allows two interconnected Ethernet network ports to independently negotiate and configure a maximum possible transmission speed and a duplex method.

Optionally, a length of the training sequence is selected based on a specified maximum clock offset.

Optionally, the training sequence is synchronized with samples of the signal. For example, thereby, it can be assured that both the training sequence and the samples of the signal have a same length.

Optionally, an equalizer and a gradient algorithm are applied to the synchronized samples.

Optionally, the gradient algorithm calculates M TR filter taps in a main equalizer.

Optionally, the sampling phase is adjusted by shifting the TR filter taps.

Optionally, the equalizer working on the M TR filter taps is updated for multiple times.

Optionally, after having provided the M TR filter taps, for providing L main equalizer taps, wherein L³M, the previously described step is repeated for multiple times. That means the equalizer working on the M TR filter taps is updated multiple times, which is carried out multiple times.

Optionally, TR is carried out using the M TR filter taps, and after having obtained the clock information, the main equalizer uses the L main equalizer taps to equalize a received signal. This may mean, for example, that after having obtained the clock information, the main equalizer works in a blind mode.

Optionally, the TR filter taps are applied for an in-phase TR filter (ITR filter).

Optionally, for providing multiple quadrature timing recovery filter taps (QTR filter taps) for a quadrature timing recovery filter (QTR filter) the method comprises a step of interpolating the TR filter taps generating a phase-shift between a timing error detector characteristic (TEDC) of the TR filter and a TEDC of the QTR filter. Thereby, filter taps for a satisfactory TR can be provided.

Optionally, the multiple QTR filter taps generate a phase-shift between the TEDC of the ITR filter and the TEDC of the QTR filter of TT/2 (Pi/2). The provided TEDCs are advantageous for providing a very satisfactory TR.

Optionally, for providing multiple optimization timing recovery filter taps (OTR filter taps) for an optimization of timing recovery, the method comprises a step of interpolating the TR filter taps generating a phase-shift between the TEDC of the TR filter and a TEDC of the OTR filter. Thus, the optimization filter taps directly build on the other TR filter taps and can therefore provide simple, accurate and refining filtering.

Optionally, the multiple OTR filter taps are provided by interpolating ITR filter taps at a phase in a region of a TEDC equilibrium point.

Optionally, the method comprises a step of unbiasing of TEDC.

Optionally, after having obtained the clock information, a sampling phase is optimized. Thus, the sampling phase is particularly optimized after having completed PFD.

Optionally, the sampling phase is varied by changing the multiple TR filter taps.

Optionally, after having applied an equalizer to samples of the signal, a mean square error (MSE) is calculated.

Optionally, the method comprises a step of changing the sampling phase by a value delta. Optionally, the method comprises the step of acquiring channel properties and the sampling phase and calculating the MSE.

Optionally, the previously described steps of calculating an MSE, changing the sampling phase by a value delta, and acquiring channel properties and the sampling phase and calculating the MSE are repeated until a minimum MSE is provided.

These and other aspects of the disclosure will be apparent from and elucidated with reference to the implementation forms described hereinafter. Individual features disclosed in the implementation forms can constitute alone or in combination an aspect of the present disclosure. Features of the different implementation forms can be carried over from one implementation form to another implementation form.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms of the present disclosure will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Fig. 1 shows a schematic drawing for illustrating a principle of timing recovery according to of the disclosure;

Fig. 2 shows a schematic drawing for illustrating a first timing recovery mode according to of the disclosure;

Fig. 3 shows a schematic drawing for illustrating a second timing recovery mode according to of the disclosure;

Fig. 4 shows a schematic drawing for illustrating a principle for calculating timing recovery filter taps according to the disclosure;

Fig. 5 shows a schematic drawing for illustrating a principle for an adjustment of a sampling phase according to the disclosure; and

Fig. 6 shows TEDCs over one unit interval for different modulation forms. DETAILED DESCRIPTION

Figure 1 shows a schematic drawing for illustrating a principle of timing recovery. The following functional units are used: an analog-to-digital conversion unit (ADC) 1 , an application specific integrated circuit (ASIC), a micro controller 2, phase detectors, which are an in-phase detector (I PD) 3a, a quadrature phase detector (QPD) 3b and an optimization phase detector (OPD) 3c, timing recovery filters, which are an in-phase timing recovery filter 4a (ITR filter, or more shortly referred by ITR FIL), a quadrature timing recovery filter 4b (QTR filter, or more shortly referred by QTR FIL), and an optimization timing recovery filter 4c (OTR filter, or more shortly referred by OTR FIL), an ATAN block 5, a TR control block 6, an equalizer ?, a voltage-controlled oscillator 8, filtering means (FIL) 9, unwrapping means 10, infinite impulse response filters 11 (HR filters, or shortly referred to by “HR”), mean square error estimation (MSE) means 19, and decision means 20, which is a decision circuit (DEC). This circuit can be e.g. a sheer (quantizer). For example, the signal after the equalizer is a non-integer value and the sheer makes decisions. Supposing one sends 0 and 1 (binary signal; PAM2), one obtains, after the equalizer a value 0.95. The sheer will output a value 1.

The ADC 1 samples an input analog electrical signal at a baud rate, i.e. one sample per symbol (1sps) is available after the analog-to-digital conversion. The ASIC works in parallel with N samples. Each of the N samples is processed with a half weighting corresponding to N/2 by the functional units from ITR FIL 4a, IPD 3a and HR 11, or QTR FIL 4b, QPD 3b and HR 11.

The timing recovery (TR) is supported by the micro controller 2. In the beginning, it works as a phase-frequency detector (PFD) and later when clock offset is acquired it works as a phase detector (PD). The TR locks at a random phase but later the sampling phase can be optimized. The TR is supported by algorithms for PD gain estimation and PD optimization. Ah phase detectors that means IPD 3a, QPD 3b, and OPD 3c are the same.

The timing recovery filters, that means ITR FIL 4a, QTR FIL 4b and OTR FIL 4c, enable clock extraction in severe intersymbol interference (ISI) channels. They are obtained by using the short training sequence. The PFD detector combines in-phase and quadrature signals to acquire clock in an ATAN block 5. The ATAN block output is described by c = atan2(a, b).

The PD output is biased by a signal d to improve clock performance when PD transfer function is asymmetrical. The TR control block 6 controls ah blocks and optimizes the TR. There is no need to mention that not ah control connections are shown in Figure 1. The novel TR scheme is reconfigurable and works in two modes. The modes are schematically shown in Figures 2 and 3.

Mode 1 is shown in Figure 2. This mode is a phase-frequency detection (PFD) mode. In PFD mode, the TR acquires a large frequency offset that can be several hundred ppm. In-phase and quadrature PDs, that means I PD 3a and QPD 3b, are the same in both modes while TR filters are different. Quadrature TR filter (QTR FIL) 4b does signal equalization and phase shift of p/4 (Pi/4) that is inaccurate because of 1sps ADC sampling rate. This will not influence the acquisition performance. The first-order HR filters 11 are used to average PD outputs before an atan2 operation in the ATAN block 5. The signal after ATAN block 5 is unwrapped to enable the PFD behavior. The block FIL 8 filters TR estimations and controls the VCO phase and frequency.

Mode 2 is shown in Figure 3. This mode is a phase detection (PD) mode. In this mode, the TR works as a PD and tracks small clock frequency and phase variations. The PD filters are the same. The power consumption in both modes is similar as HR 11 and ATAN block 5 do not consume much power, which is one operation per ASIC clock.

The TR uses the absolute PD (APD) with outputs generated by

TEDC( ) = abs(x( ) + c(t + T))[abs(x(r )) - abs(x(r + G))]

The examination of TEDCs over one-unit interval (Ul) for different modulation formats are shown in Figure 6. The signal power is normalized to 1. From there one can see that TEDC practically does not depend on PAM format. This function is symmetrical and has the sinusoidal-like shape. The TEDC is without hang up regions.

The PFD combines two signals from in-phase and quadrature branches to derive the clock control signal. The main problem is how to get samples at quadrature phase as one has only 1sps signal. One uses an ITR FIL 4a and changes filter coefficients to get clock information at the quadrature phase. In ISI-free channels, the PFD has a nonlinear TEDC while in heavy ISI channels this characteristic gets linear. The ITR FIL and QTR FIL coefficients for a heavy ISI channel are obtained by a special procedure that will be explained later. The APD TEDC is almost sinusoidal. The PFD TEDC with unwrapping is almost linear. After unwrapping PFD function is enabled.

When frequencies around the Nyquist frequency are very weak and noisy there is no any known PD that can extract clock. Therefore, we need the TR FIL to enable the clock extraction. In FTN systems, the TEDC without the TR FIL is weak and always positive or negative (no zero crossing point) so that the TR cannot lock. Using the TR FIL enables the clock extraction. More taps improve the clock quality. However, the TEDC is also biased that can cause problems in the TR, such as an instable clock, a higher cycle slip probability, or a larger self-jitter. The number of taps strongly influences the PD gain and the TR loop bandwidth. The main problems to be solved are finding TR filter taps and PD gain estimation.

Figure 4 shows a scheme for illustrating how the TR filter taps are obtained. For obtaining the TR filter taps, inter alia, the ADC 1, a buffer 2N 12, a first clock 13, a second clock 14, the equalizer 7, a gradient algorithm block 15, to which shortly is referred by the “gradient algorithm”, synchronization means 16, and a training sequence 17.

The TR filter taps can be calculated either in the microcontroller 2 or in the ASIC. In the following, the ASIC version that can be easily converted to the microcontroller 2 is explained. The TR is unlocked and frequency offset can be e.g. 100 ppm. The procedure consists of the following steps:

According to a first step, samples after ADC 1 are stored in the buffer of size 2N. Thereafter, clock 1 is disabled. The sampling phase is random.

According to a second step, the training sequence 17 is synchronized with the stored samples. The length of this sequence depends on the maximum clock offset. A good choice for 100 ppm clock offset is the sequence length of 256 symbols. After synchronization, the second clock 14 starts the equalizer 7 and gradient algorithm 15.

According to a third step, the M linear equalizer taps are set to 0 except of the central tap that is set to 1. M can be e.g. 9.

According to a fourth step, the equalizer 7 is updated in the training mode with the same input signal. The number of updates can be e.g. 500. These taps are now ready to be used in the TR filter.

According to a fifth step, the third and the fourth step are repeated for e.g. M=51 to get the main equalizer linear starting taps.

According to a sixth step, the TR is started with the derived filter taps. When the TR is locked a main equalizer uses the derived taps and works in a blind mode.

When the TR filter taps for the I PD are available, one can use the interpolation to obtain QPD and OPD taps. The QPD taps should produce a phase shift of TT/2 (Pi/2 or 1/4UI). Because one uses 1sps the interpolation will not be accurate. The QPD taps will not produce the shifted version of IPD TEDC. However, it will be satisfactory for PFD functionality. The OPD taps are obtained by interpolation at a phase very close to the TEDC equilibrium point (TR sampling phase). This phase can be e.g. TT/8 (Pi/8 or 1/16UI).

In the ideal case, OPD TEDC should be IPD TEDC shifted by 1/16UI. As one uses 1sps this curve can be shifted not exactly by 1/16UI and the amplitude of this function can be slightly changed, wherein such accuracy should be acceptable in the practical systems.

A good sampling phase for the experimental data may be, for example, -0.1563T. The TR sampling phase may be different.

To find a good sampling phase one uses the architecture shown in Fig. 5. The architecture comprises an ADC, an equalizer 7, an ITR FIL 4a, an IPD 3a, a QTR FIL 4b, a QPD 3b, filtering means (FIL) 9, a VCO 8, gradient search means 18, and mean square error estimation (MSE) means 19.

After the equalizer 7, a mean square error is calculated and stored. The sampling phase is changed by a small value D, for example by 0.01 Ul. The sampling phase change is done by interpolating the TR taps by D. The phase shift will not be D but the direction will be correct. The TR and equalizer 7 need some time to acquire sampling phase and channel conditions. After acquisition a new MSE is available. The correct direction provides the minimum MSE value. After acquiring a good sampling phase, the sampling phase adjustment circuit works in the dithering mode at very low speed.

TEDC can be biased by d (see Fig. 1) to make TR more immune to cycle slips. When the TR works in the PD mode the OPD phase can be set to p/4 (Pi/4) to measure TEDC value n(+p/4) (v(+Pi/4)). Then, the measurement is done at -TT/4 (-Pi/4) phase. The difference between these two values gives the bias value.

The disclosure has been described in conjunction with various implementation forms herein.

However, other variations to the disclosed implementation forms can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

Reference signs list

1 ADC

2 micro controller

3a I PD

3b QPD

3c OPD

4a ITR FIL

4b QTR FIL

4c OTR FIL

5 ATAN block

6 TR control block

7 equalizer

8 voltage-controlled oscillator

9 FIL

10 unwrapping means

11 MR

12 buffer 2 N

13 first clock

14 second clock

15 gradient algorithm block

16 synchronization means

17 training sequence

18 gradient search means

19 MSE means

20 decision means