Title:
METHOD FOR CALCULATING DELAY TIME OF SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY TIME CALCULATING SYSTEM
Document Type and Number:
WIPO Patent Application WO/2003/060776
Kind Code:
A1
Abstract:
A method for calculating delay time of a semiconductor integrated circuit capable of efficiently verifying a timing and a delay time calculating system. The propagation delay time of a signal path considering the in−chip variation is calculated in consideration of the variation coefficient after correction. The correction value of the variation coefficient is calculated by using a function that can approximate the propagation delay time attributed to the in−chip variation to a propagation delay time attributed to the actual in−chip variation, depending on the number of cells of the signal path. The propagation delay time has an adequate occurrence probability in the 3 &sgr range of a probability density normalized distribution.
Inventors:
ANDOU KATSUMI (JP)
Application Number:
PCT/JP2002/000113
Publication Date:
July 24, 2003
Filing Date:
January 11, 2002
Export Citation:
Assignee:
FUJITSU LTD (JP)
FUJITSU VLSI LTD (JP)
ANDOU KATSUMI (JP)
FUJITSU VLSI LTD (JP)
ANDOU KATSUMI (JP)
International Classes:
G06F17/50; (IPC1-7): G06F17/50; H01L21/82
Foreign References:
| US5365463A | 1994-11-15 | |||
| JPH035888A | 1991-01-11 | |||
| JP2001306647A | 2001-11-02 |
Other References:
Takumi HASEGAWA et al., "Dai-Kibo Kairo muke Timing Kaiseki System HEART(1) Kousoku-ka no Shuhou", Jouhou Shori Gakkai Zenkoku Taikai Kouen Ronbunshuu, Jouhou Shori Gakkai, 1987, Vol. 35, No. 3, pages 2275/2276
Attorney, Agent or Firm:
Onda, Hironori (Ohmiya-cho 2-chome Gifu-shi, Gifu, JP)
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