The solutions disclosed herein relate generally to power amplifiers, and more particularly to improving the efficiency and linearity of power amplifiers.

BACKGROUND

The performance of a wireless transceiver relies heavily on the performance, e.g., linearity, efficiency, etc., of the amplifiers used by the wireless transceiver to amplify signals, e.g., for subsequent transmission. To achieve good power efficiency and linearity, a power amplifier may comprise a plurality of amplifier cells that each operate as B-class amplifiers. For example, the input bias point for each amplifier cell is typically set close to the amplifier cut-off to achieve a high linearity across the entire input voltage range characteristic of B- class operation. Typical B-class amplifier cells, however, are sensitive to process variations. For example, process variations incurred during the manufacture of the amplifier cells cause large gain step variations between amplifier cells, especially when operating with low gain levels (e.g., due to a small input signal and/or due to the power amplifier having only a small number of active amplifier cells.

Conventional solutions to this problem may adjust, for example, the bias point of the active power amplifier cells such that they operate as an A-class amplifier when operating with low gain levels. In so doing, the conventional solution improves the linearity of the power amplifier for these low gain level situations. However, because A-class power amplifiers are significantly less efficient than B-class power amplifiers, this conventional solution increases the already problematic efficiency problems.

Thus, there remains a need for improved power amplifier solutions that achieve a desired linearity and efficiency even when operating with low gain levels.

SUMMARY

The solution disclosed herein improves the linearity and efficiency of a power amplifier comprising a plurality of amplifier cells, especially when only a small number of the plurality of amplifier cells is active. To that end, a bias control word is selected from a predetermined bias table for each of the active amplifier cells. An average of the selected bias control words is then used to bias an input stage of each active amplifier cell.

One exemplary embodiment provides a method of reducing gain step error and improving linearity of a plurality of power amplifiers, wherein an operational point of each power amplifier during the operational phase is set such that an average amplifier current increases with increasing amplitude of an RF signal applied to the input stage of the power amplifier. The method comprises identifying which one or more of the plurality of power amplifiers are active during an operational phase of the plurality of power amplifiers. The method further comprises selecting a bias control word corresponding to each identified active power amplifier from a bias table, the bias table comprising a bias control word for each power amplifier, averaging the selected bias control words to determine an input bias control word, and biasing an input stage of each active power amplifier according to the input bias control word.

In another exemplary embodiment, a bias circuit reduces a gain step error and improves a linearity of a plurality of power amplifiers. An operational point of each power amplifier during the operational phase is set such that an average amplifier current increases with increasing amplitude of an RF signal applied to the input stage of the power amplifier. The bias circuit comprises a configuration circuit and a selection circuit. The configuration circuit is configured to identify which one or more of the plurality of power amplifiers are active during an operational phase of the plurality of power amplifiers. The a selection circuit is configured to select a bias control word corresponding to each identified active power amplifier from a bias table, the bias table stored in a memory operatively connected to the bias circuit and comprising a bias control word for each power amplifier. The selection circuit is further configured to average the selected bias control words to determine an input bias control word and bias an input stage of each active power amplifier according to the input bias control word.

Another exemplary embodiment provides an amplifier system comprising a plurality of power amplifiers, a memory, and a bias circuit. An operational point of each power amplifier during the operational phase is set such that an average amplifier current increases with increasing amplitude of an RF signal applied to the input stage of the power amplifier. The memory is configured to store a bias table comprising a bias control word for each of the plurality of power amplifiers. The bias circuit is configured to reduce a gain step error and improve a linearity of the plurality of power amplifiers. The bias circuit comprises a configuration circuit and a selection circuit. The configuration circuit is configured to identify which one or more of the plurality of power amplifiers are active during the operational phase of the plurality of power amplifiers. The selection circuit is configured to select the bias control word corresponding to each identified active power amplifier from the bias table. The selection circuit is further configured to average the selected one or more bias control words to determine an input bias control word and bias an input stage of each active power amplifier according to the input bias control word.

Another exemplary embodiment provides a method of generating one or more bias tables for a plurality of power amplifiers. An operational point of each power amplifier during the operational phase is set such that an average amplifier current increases with increasing amplitude of an RF signal applied to the input stage of the power amplifier. The method comprises determining an optimal bias control that optimizes a linearity of the plurality of power amplifiers when all power amplifiers are active, generating an initial bias table comprising an initial bias control word for each power amplifier determined when only that power amplifier is active, and generating the one or more bias tables based on the optimal bias control word and the initial bias table.

In another exemplary embodiment, calibration system is configured to generate one or more bias tables for a plurality of power amplifiers. An operational point of each power amplifier during the operational phase is set such that an average amplifier current increases with increasing amplitude of an RF signal applied to the input stage of the power amplifier. The calibration system comprises an optimization circuit and a bias calibration circuit. The optimization circuit is configured to, when all power amplifiers are active, determine an optimal bias control word that optimizes a linearity of the plurality of power amplifiers. The bias calibration circuit is configured to generate an initial bias table comprising an initial bias control word for each power amplifier determined when only that power amplifier is active, and generate the one or more bias tables based on the optimal bias control word and the initial bias table.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a block diagram for a basic power amplifier array.

Figure 2 shows simulation results demonstrating the gain step error problems of conventional power amplifier arrays.

Figure 3 shows a block diagram of an amplifier system including a power amplifier array, a bias circuit, and a calibration circuit according to one exemplary embodiment.

Figure 4 shows an exemplary method for biasing the active amplifier cells of the power amplifier array of Figure 3.

Figure 5A shows an exemplary method for generating the bias table(s) used to bias the active amplifier cells.

Figure 5B shows an exemplary method for generating the initial bias table(s) used to generate the bias table(s).

Figure 6 shows a block diagram of a bias calibration circuit according to one exemplary embodiment.

Figure 7 shows simulation results of the gain mismatch when the calibration solution presented herein is used versus when it is not used.

Figures 8A and 8B show simulation results of the linearity when the calibration solution presented herein is used versus when it is not used. DETAILED DESCRIPTION

Controlling the linearity and efficiency of a power amplifier in a transceiver is critical to improving the performance of the transceiver as a whole. As used herein the term "power amplifier" refers to any amplifier that outputs more power than applied at the input. In some embodiments, the power amplifier may comprise a pre-power amplifier (e.g., an amplifier used before additional amplification to boost an input signal power without degrading the signal-to-noise ratio), an amplifier cell in a power amplifier array of amplifier cells (e.g., an array of pre-power amplifier cells), the last amplifier before the antenna of a wireless transceiver, etc. It will be appreciated, however, that the power amplifier discussed herein could be any amplifier used to increase the power of an input signal.

Figure 1 shows a basic block diagram of a power amplifier (PA) array 100 suitable for a wireless transmitter, where the PA array 100 comprises a plurality of power amplifiers, also referred to herein as amplifier cells 1 10 (e.g., as shown in Figure 3). PA array 100 activates one or more of the amplifier cells 1 10 depending on the signal strength requirements of the transmitter output signal (TX OUT). The positive and negative input stages of each active amplifier cell are biased according to positive and negative bias words, respectively.

Exemplary amplifier cells 1 10 include class B, class AB, and class C amplifier cells, where an operational point of each amplifier cell 1 10 is set such that the average amplifier current increases with increasing amplitude of an RF input signal applied to an input stage of the amplifier cell 1 10.

The effects of manufacturing process variations cause a relatively high (and undesirable) gain step variation between the amplifier cells 1 10. When a large number of amplifier cells 1 10 of the PA array 100 are active, this gain step variation has only a minor impact on the linearity and efficiency of the PA array 100. When only a small number (e.g., less than a third) of the amplifier cells 1 10 are active, however, the gain step variation can have a significant negative effect on the overall performance of the PA array 100. The solution disclosed herein seeks to reduce the effects of the gain step variation between the active amplifier cells 1 10, and thus to improve the linearity and efficiency.

Figures 2A-2C demonstrate the gain step variations between 100 different amplifier cells 1 10 when the input bias current is kept constant (Case 1 , Figure 2A) and when the input voltage is kept constant (Case 2). Case 2 results in a significant input bias current variation as shown in Figure 2A. Figure 2B shows the Case 1 and Case 2 gain step variations by showing the transconductance for each of the 100 different amplifier cells 1 10, while Figure 2C provides the same data in dBs. As shown in Figures 2B and 2C, the gain step variation is less when the input bias current is kept constant (Case 1 ) than it is when the input bias voltage is kept constant (Case 2). Figures 2A-2C therefore demonstrate the desirability of maintaining the same average bias current per unit cell across the entire gain range. This is especially helpful when the number of active amplifier cells 1 10 is small, as this scenario tends to exacerbate the gain step variation problem.

Figure 3 shows an exemplary block diagram for an amplifier system 10 comprising a bias circuit 200, and corresponding memory 300, operatively connected to the PA array 100. Bias circuit 200 biases the input stage of each active amplifier cell 1 10 in the PA array 100 so as to reduce the gain step error, and therefore to improve the linearity and efficiency of the PA array 100. To that end, bias circuit 200 comprises configuration circuit 210 and selection circuit 220. The configuration circuit 210 identifies which of the amplifier cells 1 10 in the PA array 100 are active during an operational phase of the amplifier system 10.

Memory 300 stores one or more bias tables 310, where each bias table includes a predetermined bias control word for each amplifier cell 1 10. Selection circuit 220 determines and applies the appropriate bias control word to the input stage of each active amplifier cell 1 10 based on the bias control words in the bias table(s).

Figure 4 shows an exemplary method 400 executed by the bias circuit 200. The configuration circuit 210 identifies which of the amplifier cells 1 10 in the PA array 100 are active during an operational phase of the PA array 100 (block 410). The selection circuit 220 selects the bias control word from the corresponding bias table 310 for each identified active amplifier cell 1 10 (block 420), averages the selected bias control word to determine an input bias control word (block 430), and biases the input stage of each active amplifier cell 1 10 according to the input bias control word (block 440).

For example, assume PA array 100 includes thirty-two amplifier cells 1 10, and configuration circuit 210 identifies the first, fifth, and tenth amplifier cells 1 10 as active.

Selection circuit 220 selects the bias control words corresponding to the first, fifth, and tenth amplifier cells 1 10 from bias table(s) 310, e.g., BCW(\) , BCW (5) , and BCW (10) . The selection circuit 220 then averages the selected bias control words to determine the input bias control word {BCW _input ), e.g., BCW _input = / ₃ (BCW (l) + BCW (5) + BCW (10)) , and uses the input bias control word to bias each input stage of the first, fifth, and tenth amplifier cells 1 10.

For embodiments where each amplifier cell 1 10 comprises a positive half-cell 1 12 and a negative half-cell 1 14 (Figure 6), memory 300 stores a positive half-cell bias table 312 and a negative half-cell bias table 314. The positive half-cell bias table 312 stores a predetermined bias control word for the positive half-cell 1 12 of each amplifier cell 1 10, and the negative half-cell bias table 314 stores a predetermined bias control word for the negative half-cell 1 14 of each amplifier cell 1 10. Using the same example as above, the selection circuit 220 selects the bias control words corresponding to positive half-cells 1 12 for the first, fifth, and tenth amplifier cells 1 10 from the positive half-cell bias table 312, e.g., BCW (l) , BCW (5) , and BCW (10) , and selects the bias control words corresponding to the negative half-cells 1 14 for the first, fifth, and tenth amplifier cells 1 10 from the negative half-cell bias table 312, e.g., BCW _N (l) , BCW _N (5) , and BCW _N (10) . The selection circuit

220 then averages the selected positive half-cell bias control words to determine the positive half-cell input bias control word { BCW _T ), e.g., A ¹ (BCW _P (\) + BCW _P (5) + BCW _P (\ 0)) , and uses the positive half-cell input bias control word to bias the input stage of the positive half-cell 1 12 of each of the first, fifth, and tenth amplifier cells 1 10. Similarly, the selection circuit 220 averages the selected negative half-cell bias control words to determine the positive half-cell input bias control word ( BCW _INPUT , _N ), e.g., BCW _INPUT , _N = ¼ (BCW _N (l) + BCW _N (5) + BCW _N (10)) , and uses the negative half-cell input bias control word to bias the input stage of the negative half-cell 114 of each of the first, fifth, and tenth amplifier cells 110.

More generally, if j of the M amplifier cells 1 10 are active, the selection circuit 220 determines the positive half-cell input bias control word according to: BCW _INPUTIP = -∑BCW _p (i) , (1 )

J

and determines the negative half-cell input bias control word according to:

BCW _INPUT!LL = -∑BCW _n (i) . (2)

J

Selection circuit 220 then, for each active amplifier cell 110, applies the determined positive half-cell input bias control word BCW _T to the input stage of each positive half-cell 112, and applies the determined negative half-cell input bias control word BCW _{T N} to the input stage of each negative half-cell 1 14.

The above solution is described in terms of a basic PA array 100 comprising a plurality of amplifier cells 1 10. In some embodiments, a first half of the amplifier cells 1 10 in the PA array 100 comprise ln-phase amplifier cells 1 10 configured to amplify ln-phase radio frequency (RF) signals, while a second half of the amplifier cells 1 10 in the PA array 100 comprise Quadrature amplifier cells 110 configured to amplify Quadrature RF signals. In this case, memory 300 stores at least one ln-phase bias table 310, each of which comprises an ln-phase bias control word for each of the ln-phase amplifier cells 1 10. Similarly, memory 300 stores at least one Quadrature bias table 310, each of which comprises a Quadrature bias control word for each of the Quadrature amplifier cells 110. The selection circuit 220 then selects the bias control words for the active ln-phase and/or Quadrature amplifier cells

1 10 from the ln-phase and Quadrature bias tables 310. Selection circuit 220 biases the active ln-phase amplifier cells 1 10 according to an input ln-phase bias control word determined by averaging the selected ln-phase bias control words. Similarly, the selection circuit 220 biases the active Quadrature amplifier cells 1 10 according to an input Quadrature bias control word determined by averaging the selected Quadrature bias control words.

Further, if the ln-phase and Quadrature amplifier cells 1 10 have positive and negative half-cells, additional bias tables 310 are stored in memory 300 for the positive and negative half-cells. More particularly, memory 300 may include:

• a positive ln-phase bias table comprising a bias control word for each positive half- cell 1 12 of each ln-phase amplifier cell 1 10;

· a negative ln-phase bias table comprising a bias control word for each negative half- cell 1 14 of each ln-phase amplifier cell 1 10;

• a positive Quadrature bias table comprising a bias control word for each positive half- cell 1 12 of each Quadrature amplifier cell 1 10; and

• a negative Quadrature bias table comprising a bias control word for each negative half-cell 1 14 of each Quadrature amplifier cell 1 10;

In this case, the selection circuit 220 selects and averages the appropriate bias control words from the appropriate bias tables for each active amplifier cell 1 10.

The bias control words stored in the bias table(s) 310 are predetermined, and thus available for use during the amplifier system's operational phase. In one embodiment, such bias control words are predetermined during a calibration phase. Such a calibration phase typically occurs before the operational phase. During the calibration phase, a calibration circuit 500 (Figure 3) is operatively connected to the PA array 100 and memory 300 to determine and store each bias control word for each bias table 310 in memory 300.

Figure 3 shows a block diagram of one exemplary calibration circuit 500 comprising an optimization circuit 510 and a bias calibration circuit 520. Optimization circuit 510 determines an optimal bias control word when all amplifier cells 1 10 are active, where the optimal bias control word optimizes the linearity of the amplifier cells 1 10. The bias calibration circuit 520 generates an initial bias control word for each of the amplifier cells 1 10 when only that amplifier cell 1 10 is active, and determines the bias control word for that amplifier cell 1 10 based on the initial bias control word and the optimal bias control word. The bias control word for the active amplifier cell 1 10 is then stored in the corresponding bias table 310 in memory 300. The bias calibration circuit 520 repeats this process for each of the amplifier cells 1 10.

Figures 5A and 5B show exemplary processes executed by the calibration circuit 500 to generate the positive and negative half-cell bias tables 312, 314 stored in memory 300. It will be appreciated the calibration process does not require the steps shown in Figures 5A or 5B be executed in the order shown in Figures 5A and 5B.

Figure 5A shows one exemplary process executed by the calibration circuit 500. The optimization circuit 510 determines the optimal bias control word for each of the positive and negative half-cells 312, 314 (block 610). The bias calibration circuit 520 generates one or more initial bias tables (block 620), where each initial bias table comprises an initial bias control word for one of the plurality of amplifiers determined when only that power amplifier is active. The bias calibration circuit 520 also generates one or more bias tables based on the optimal bias control word and the one or more initial bias tables (block 630).

For example, the optimization circuit 510 may determine the optimal bias control word by activating all of the amplifier cells 1 10 in the PA array 100 and identifying the bias control word that optimizes the linearity of the output of the PA array 100. For example, optimization circuit 510 may sequentially step the positive half-cell bias control words used to bias the input stage of the positive half-cell 1 12 of each amplifier cell 1 10, sequentially step the negative half-cell bias control words used to bias the input stage of the negative half-cell 1 14 of each amplifier cell 1 10, and measure the output of each amplifier cell 1 10, e.g., using an on-chip measurement receiver, for each applied bias control word. The optimization circuit 510 then selects the positive and negative half-cell bias control words that produced the most linear output as the optimal bias control word for the positive and negative half-cells 1 12, 1 14. After the optimization circuit 510 finishes, the calibration circuit 500 deactivates the amplifier cells 1 10.

Figure 5B shows one exemplary process 620 for generating the initial bias table(s), where each amplifier cell 1 10 includes a positive half-cell 1 12 and negative half-cell 1 14. To that end, bias calibration circuit 520 activates a first half-cell, e.g., the negative half-cell 1 14, of one of the amplifier cells 1 10 (block 621 ), e.g., a reference amplifier cell, and initializes a counter m to M (block 622), where the PA array 100 includes M amplifier cells 1 10. The bias calibration circuit 520 then activates the other (second) half-cell of the m ^th amplifier cell 1 10, e.g., the positive half-cell 1 12 (block 623). It will be appreciated that the counter m of Figure 5B represents only one way to sequentially determine the initial bias control words for each amplifier cell 1 10. Other ways may alternately be used. For example, m may be initialized to zero, and subsequently may be incremented.

The bias calibration circuit 520 then biases the input stage of the negative half-cell 1 14 of the reference amplifier cell 1 10 according to a reference bias control word, while varying a bias control word used to separately bias the input stage of the active positive half- cell 1 12 (while all other positive half-cells 1 12 are inactive) until the output of the biased positive half-cell 1 12 matches that of the reference-biased negative half-cell 1 14 (block 624). Each bias control word that produces a positive half-cell output matching that of the reference-biased negative half-cell 1 14 is identified as an initial bias control word for the corresponding positive half-cell 1 12. The active positive half-cell 1 12 of the m ^ih amplifier cell 1 10 _m is then deactivated, m is decremented (block 625), and the process repeats for the positive half-cell 1 12 of the next amplifier cell (blocks 623-625), e.g., the (m - l) ^th amplifier cell 1 10 _m -i , until m = 0 (blocks 626 and 627).

For example, the m = 1 amplifier cell 1 10 may be used as the reference amplifier cell, such that the negative half-cell 1 12 of the m = 1 amplifier cell 1 10 is biased according to the reference bias control word; all other negative half-cells 1 14 are inactive. The bias control word that produces a positive half-cell output for the m = 1 amplifier cell 1 10 matching that of the reference-biased negative half-cell 1 14 when all other positive half-cells are inactive is identified as an initial bias control word for the positive half-cell 1 12 of the m = 1 amplifier cell. The bias control word that produces a positive half-cell output for the positive half-cell 1 12 of the m = 2 amplifier cell 1 10 matching that of the reference-biased negative half-cell 1 14 (of the m = 1 amplifier cell 1 10) when all other positive half-cells are inactive is identified as an initial bias control word for the positive half-cell 1 12 of the m = 2 amplifier cell 1 10. This process continues until the initial bias control word is determined for each positive half-cell 1 12.

The bias calibration circuit 520 does a similar process to determine the initial bias control word for each negative half-cell 1 12. In this case, the "first" half-cell is the positive half-cell 1 12 of the reference amplifier cell 1 10, and the "second" half-cell is the negative half-cell 1 14 of any one of the amplifier cells 1 10. More particularly, the bias calibration circuit 520 activates the first half-cell, e.g., the positive half-cell 1 12, of one of the amplifier cells 1 10 (block 621 ), e.g., a reference amplifier cell, and initializes the counter m to M (block 622). The bias calibration circuit then activates the other (second) half-cell of the m ^th amplifier cell 1 10, e.g., the positive half-cell 1 12 (block 623). Bias calibration circuit 520 then biases the input stage of the positive half-cell 1 12 of the reference amplifier cell according to the reference bias control word, while varying a bias control word used to separately bias the input stage of the active negative half-cell 1 14 (when all other negative half-cells 1 14 are inactive) until the output of the biased negative half-cell 1 14 matches that of the reference- biased positive half-cell 1 12 (block 624). Each bias control word that produces a negative half-cell output matching that of the reference-biased positive half-cell 1 12 is identified as an initial bias control word for the corresponding negative half-cell 1 14. The active negative half-cell 1 14 of the m ^th amplifier cell 1 10 _m is then deactivated, m is decremented (block 625), and the process repeats for the negative half-cell 1 14 of the next amplifier cell (blocks 623-625), e.g., the (m - l) ^th amplifier cell 1 10 _m- i , until m = 0 (blocks 626 and 627). For example, the m = 1 amplifier cell 1 10 may be used as the reference amplifier cell, such that the positive half-cell 1 14 of the m = 1 amplifier cell 1 10 is biased according to the reference bias control word; all other positive half-cells 1 12 are inactive. The bias control word that produces a negative half-cell output for the m = 1 amplifier cell 1 10 matching that of the reference-biased positive half-cell 1 14 when all other positive half-cells are inactive is identified as an initial bias control word for the negative half-cell 1 12 of the m = 1 amplifier cell. The bias control word that produces a negative half-cell output for the negative half-cell 1 12 of the m = 2 amplifier cell 1 10 matching that of the reference-biased positive half-cell 1 14 (of the m = 1 amplifier cell 1 10) when all other negative half-cells are inactive is

identified as an initial bias control word for the negative half-cell 1 12 of the m = 2 amplifier cell 1 10. This process continues until the initial bias control word is determined for each negative half-cell 1 12.

The bias calibration circuit 520 generates the positive and negative half-cell bias tables based on the corresponding optimal and initial bias control words (block 630). For example, bias calibration circuit 520 generates a bias control word for the positive half-cell 1 12 of each amplifier cell 1 10 based on the optimal bias control word and each of the initial bias control words determined for all of the positive half-cells 1 12. Similarly, bias calibration circuit 520 generates a bias control word for the negative half-cell 1 14 of each amplifier cell 1 10 based on the optimal bias control word and each of the initial bias control words

determined for all of the negative half-cells 1 14.

For example, the bias calibration circuit 520 may generate the bias control word for the positive half-cell 1 12 of the m ^th amplifier cell 1 10 _m according to:

1 M

BCW _p {m) = BCW^ _p {m) + BCW _opt,p -—∑BCW _Mt,p (m) , (3)

M m=l

where BCW _{init p} (m) represents the initial positive half-cell bias control word determined for the m ^th amplifier cell 1 10 _m , and BCW represents the optimal bias control word

determined for the positive half-cells 1 12. Similarly, the bias calibration circuit 520 may generate the bias control word for the negative half-cell 1 14 of the m ^ih amplifier cell 1 10 _m according to:

1 M

BCW _n (m) = BCW _{ini n} {m) + BCW _opt,n -—∑BCW _Mt,n (m) (4)

m=l

where BCW _{init n} (m) represents the initial negative half-cell bias control word determined for the m ^th amplifier cell 1 10 _m , and BCW _n represents the optimal bias control word

determined for the negative half-cells 1 14. Figure 6 shows an exemplary block diagram for the bias calibration circuit 520 when determining the initial bias control words for the positive and negative half-cells of one of the amplifier cells 1 10 according to Figure 5B. Bias calibration circuit 520 comprises a switch 522, processing circuit 524, and comparator 526. While switch 522 is shown as being part of the bias calibration circuit 520 in Figure 6, it will be appreciated that it may simply be part of the amplifier cell circuitry. During the operational phase, switch 522 is closed to tie the half-cell outputs together and to a supply voltage VDD. When determining the bias control word for each half-cell, however, bias calibration circuit 520 opens switch 522 to disconnect the half-cell outputs from each other and from VDD. It will be appreciated that switch 522 is not limited to a single switch, but may represent any number of switches necessary to make the desired connections. Processing circuit 524 biases one of the half-cells 1 12, 1 14 of one amplifier cell 1 10 according to a reference bias control word while stepping the other half-cell 1 14, 1 12 of the amplifier cells 1 10 (when only one is active at a time) through a series of bias control words. Comparator 526 compares the output generated by the half-cell 1 12, 1 14 biased according to the reference bias control word with the output generated by the other half-cell 1 14, 1 12 biased according to one of the possible bias control words. Processing circuit 524 evaluates the comparator outputs to identify the initial bias control word producing the half-cell output matching that of the half-cell 1 12, 1 14 biased according to the reference bias control word, and stores the identified initial bias control word either in a temporary memory (not shown) associated with the processing circuit 524 or in memory 300. The bias calibration circuit 520 repeats these operations for each of the other half-cells 1 14, 1 12.

When the PA array 100 comprises ln-phase and Quadrature amplifier cells 1 10, each having a positive half-cell 1 12 and a negative half-cell 1 14, the above-described process is separately performed for the ln-phase and Quadrature amplifier cells 1 10 to produce a positive half-cell ln-phase bias table, a negative half-cell ln-phase bias table, a positive half- cell Quadrature bias table, and a negative half-cell Quadrature bias table. If the PA array 100 does not have different types of amplifier cells, however, the above-described process is performed to produce a positive half-cell bias table and a negative half-cell bias table.

While the above describes the determination of the bias control words stored in the bias tables 310 during a calibration phase that occurs before an operational phase, it will be appreciated that the calibration circuit 500 may additionally adjust the bias control words determined during the calibration phase by determining one or more new bias control words for each bias table 310 during the operational phase. When the calibration circuit 500 determines a new bias control word during the operational phase, the calibration circuit 500 replaces the predetermined bias control word (determined during the calibration phase) with the new bias control word in the appropriate table 310. In so doing, the calibration circuit 500 may account/adjust for environmental/temperature/lifetime effects on the amplifier cells 1 10, and therefore, may improve the linearity and efficiency of the amplifier cells 1 10. For example, as a high output circuit ages or experiences high temperatures, the junction temperature of one or more of the transistors in the circuit may increase sufficiently to cause a new mismatch. The calibration circuit 500 may then be used to determine a new bias control word for the affected circuit(s) during non-operational times of the circuit, e.g., during non-transmission times of an amplifier circuit.

Figures 7 and 8A-8B show simulation results that illustrate the benefits of the solution disclosed herein. Figure 7 show the maximum gain mismatch between two amplifier cells 1 10 when the calibration solution disclosed herein is not used (Case A) versus when it is used (Case B). As shown by Figure 7, the calibration solution disclosed herein significantly reduces the gain mismatch, e.g., by 0.2 - 0.5 dB.

Figures 8A and 8B show the linearity achieved when the solution is used (Figure 8A) versus when it is not used (Figure 8B) by plotting the differential transconductance for both cases across a large RF input signal range. In both figures, each line represents the linearity associated with a different number of active amplifier cells 1 10. As shown in Figure 8A, the linearity achieved using the solution presented herein remains uniform regardless of the number of active amplifier cells 1 10, which is not true for the simulation shown in Figure 8B, which applies the same bias voltage regardless of the number of active amplifier cells 1 10. Thus, the solution presented herein improves the efficiency and linearity of a PA array regardless of the number of active amplifier cells 1 10.

Various elements disclosed herein are described as some kind of circuit, e.g., a bias circuit 200, configuration circuit 210, selection circuit 220, calibration circuit 500, optimization circuit 510, bias calibration circuit 520, processing circuit 524, etc. Each of these circuits, as well as PA array 100, amplifier cells 1 10, switch 522, and comparator 526 may be embodied in hardware and/or in software (including firmware, resident software, microcode, etc.) executed on a controller or processor, including an application specific integrated circuit (ASIC). Further, memory 300 may comprise any type of known memory, including but not limited to a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EEPROM or Flash memory), etc.

The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.