METHOD FOR CONNECTING A SUBSTRATE ARRANGEMENT TO AN ELECTRONIC COMPONENT USING A PRE-FIXATION AGENT APPLIED ONTO A CONTACTING MATERIAL LAYER, CORRESPONDING SUBSTRATE ARRANGEMENT, AND METHOD FOR PRODUCING SAME

Title:

Document Type and Number:

WIPO Patent Application WO/2017/060140

Kind Code:

A3

Abstract:

The invention relates to a method for producing a substrate arrangement (10, 10") for connecting to an electronic component (30), comprising the steps of: providing a substrate (11) that has a first side (12) and a second side (13), applying a contacting material layer (15) to the first side (12) of said substrate (11), and applying a pre-fixation agent (18) to at least some sections of a side (16) of the contacting material layer (15) that faces away from said substrate (11). The invention also relates to a corresponding substrate arrangement (10, 10") and to a corresponding method for connecting at least one electronic component (30) to the substrate arrangement (10, 10"). The claimed measures provide for sufficient handling strength during transportation from the place of assembly to the place of connection. The contacting material layer (15) should preferably be applied across the whole surface, or close to the whole surface, on the first side (12) of the substrate (11). The substrate (11), with the applied contacting material layer (15) and the applied pre-fixation agent (18), can be positioned detachably on a carrier (20). When connecting to the electronic component (30, 30'), the substrate arrangement (10, 10") is sintered, crimped, soldered and/or bonded thereto. The substrate (11) can be a metal sheet or a metal strip section, particularly a copper sheet or a copper strip section, a lead frame, a DCB substrate or a PCB substrate. The electronic component (30) can be a semiconductor, a DCB substrate or a PCB substrate.

More Like This:

JPS5950116	[Title of the Invention] Diffusion . alloy type semiconductor device
JPS6035244	[Title of the device] The substrate for integrated circuit element loading

Inventors:

HINRICH ANDREAS (DE)
DUCH SUSANNE (DE)
MIRIC ANTON (DE)
SCHÄFER MICHAEL (DE)

Application Number:

PCT/EP2016/073102

Publication Date:

June 01, 2017

Filing Date:

September 28, 2016

Export Citation:

Click for automatic bibliography generation Help

Assignee:

HERAEUS DEUTSCHLAND GMBH & CO KG (DE)

International Classes:

H01L21/58; H01L21/48; H01L21/60; H01L21/683; H01L23/373; H01L23/488; H05K3/32; H05K3/34; H05K3/36; H01L23/14; H01L23/495

Domestic Patent References:

WO2014136683A1	2014-09-12
WO2014049059A2	2014-04-03
WO2008006340A1	2008-01-17

Foreign References:

EP2390904A2	2011-11-30
DE102014109766B3	2015-04-02
US20110310568A1	2011-12-22
EP2428293A2	2012-03-14
EP1684340A2	2006-07-26
DE202015001441U1	2015-03-18

Other References:

BAI G: "Low-Temperature Sintering of Nanoscale Silver Paste for Semiconductor Device Interconnection", October 2005 (2005-10-01), pages 1 - 195, XP009166994, Retrieved from the Internet

Attorney, Agent or Firm:

KILCHERT, Jochen (DE)

Download PDF:

View/Download PDF PDF Help

Previous Patent: POLYPROPYLENE COMPOSITIONS FOR AUTOMOTIVE APPLICATIONS

Next Patent: ELECTROMAGNETIC SWITCH VALVE