METHOD OF DETECTING DEFECTS IN AN INTEGRATED CIRCUIT

Field of the Invention

The present invention relates to a method of detecting defects in an integrated circuit.

Background of the Invention

When making an integrated circuit (which may also be referred to as an, IC, chip or device) , a design of the IC is made using, for example, CAD tools. A reticle or mask is then produced for the IC design and then photolithography is used to transfer features from the reticle or mask to a die (semiconductor wafer) .

Various techniques are used to reduce the level of defects in the resultant die. For instance, prior to the production of the reticle, the design may be optimised using optical proximity correction (OPC) . This optimisation process amends the physical layout in order to avoid optical distortions that may cause failures of the device. Isolating and fixing errors at this early design stage reduces the number of design and test cycles required to produce the finished device and so leads to a more efficient manufacturing process.

Once the reticle is produced and test dies have been manufactured, these test dies may be visually inspected for physical defects using optical or scanning electron microscope (SEM) techniques. Obviously, individually inspecting each feature on a multi-million gate device is unfeasible. Therefore, techniques are used to generate potential defect sites that may require individual analysis.

In one such technique individual defects are highlighted by deliberately producing a lower quality die and comparing this with a separate die manufactured under more optimum conditions. The two dies produced under these different conditions are then compared and physical differences in the features are isolated. Where significant changes to the features are detected, it is possible to determine that a defect is likely to occur at that location on the device. It is these areas that will require additional visual analysis. In this way the number of sites that requires analysis may be reduced but this may still result in a considerable number of sites requiring a detailed and time consuming analysis. The comparison of the two dies is usually carried out using specialized hardware and computer software to analyse images of the dies. The die-die comparison technique is also known as Process Window Qualification (PWQ) and the defects introduced by the production of pairs of dies fabricated under different conditions are also known as process window (PW) errors. Typically, pairs of dies are produced by varying the focus of the image of the reticle on the wafer to obtain dies with different feature characteristics. This die-die comparison technique may require several pairs of dies before any significant changes can be found. US 6,902,855 describes die-die comparison where dies are produced under different conditions.

US 6,826,735 describes a method of evaluating defect data by comparing the locations of defects with the design. US 6,140,140 describes a method for investigating two portions of a semiconductor wafer differently according to a first and a second process in order to isolate defects.

US 6,701,004 describes a die-die comparison to detect locations of defects.

Typically, a large number of defects are identified using the die-die comparison techniques and each of these defects requires analysis effort to determine if and how they are to be fixed. This can slow the IC test process and lead to delays in manufacturing of the completed device. There may be too many defects to investigate and this could lead to important defects being missed, whilst less critical defects are investigated in more detail. There may be many similar defects that are found and that results in duplication of effort when analysing each of these similar defects .

Several pairs of dies may be produced and a comparison of each of these pairs may be made. It may be found that a particular pair of dies results in too few or even no defects at all, whereas another pair of dies fabricated under different conditions (e.g. with the reticle at different focal planes) to the first pair results in too many defects. Each detected defect must be investigated in order to determine whether or not it will be critical to the operation of the device and fixed if necessary.

In order to investigate each defect, the location of the defect is usually provided using a coordinate system. In order to investigate each defect the pair of dies must be imaged, usually using a separate imaging device, e.g. a SEM, from the device used for obtaining the initial die image used in the comparison process. The two different instruments may have their own coordinate systems for locating features on the die. Furthermore, physically moving the dies from one instrument to another creates an alignment problem as there may be no correlation between the

coordinate system of the PWQ analysis device and the second imaging device (SEM) .

It is therefore desirable to provide an improved method for investigating the defect data. It is further desirable to provide an improved method for locating the identified defects.

Summary of the Invention

In accordance with a first aspect of the present invention, there is provided a method for detecting defects in an integrated circuit as described in claim 1.

In accordance with a second aspect of the present invention, there is provided a method for detecting defects in an integrated circuit as described in claim 19.

The claimed invention has a number of advantages over the prior art. In particular, the number of defects that need to be analysed may be reduced and so reduce the time required to test the device. After prioritisation of the defects it is possible to analyse the most important defects first and so identify significant defects at an earlier stage .

Feeding back the results of the comparison data to the OPC design stage may improve the quality of the resultant device and improve the efficiency of the design process.

Ignoring repeated defects further reduces the number of defects requiring analysis and also speeds up the testing stage .

Categorising defects allows similar defects to be analysed together and so highlights any patterns or systematic errors in the design.

The use of alignment targets allows easier alignment of the dies after transferring from one instrument to another. This may also allow for further automation in the testing process . The invention may be implemented within a computer program and such a computer program may be loaded onto a computer. This provides a further aid to the testing procedure.

Brief description of the Figures

The present invention may be put into practice in a number of ways and a preferred embodiment will now be described by way of example only and with reference to the accompanying drawings, in which:

FIG. 1 shows a flow diagram of the method steps for finding defects in an integrated circuit according to a first aspect of the present invention;

FIG. 2 shows a flow diagram of the method steps for finding defects in an integrated circuit according to a second aspect of the present invention;

FIG. 3 shows the layout of two similar wafer dies produced under different conditions and including highlighted critical defects;

FIG. 4 shows the layout of two similar wafer dies produced under different conditions and including highlighted non-critical defects; and

FIG. 5 shows a schematic diagram of three deliberate defects to be introduced into an integrated circuit and the effect on the deliberate defects when the focus of a reticule image forming the defects on a die is changed.

It should be noted that the figures are illustrated for simplicity and are not necessarily drawn to scale.

Detailed description of a preferred embodiment

FIG. 1 shows a flow chart describing a method 10 for detecting defects in an integrated circuit according to a first aspect of the present invention.

As described above with respect to the prior art, the method steps shown in FIG. 1 include the production of a pair of dies produced under different conditions. As shown in FIG. 1 the different conditions relate to the focus of the reticle image on the wafer die.

In step 20 a first die is produced by focussing an image of a reticle at a particular plane with respect to a wafer. Then in step 30 a second die is produced by using the same reticle but by focussing its image at a different plane with respect to the wafer. The displacement between the focal planes used to form the two dies is 0.2 um (microns) . Then, at step 40 the two dies are compared.

This is carried out by optically imaging the dies and using computer software techniques to compare differences in the resultant optical images. Such comparison may be carried out by a high resolution imaging system such as the 23xx series high-resolution inspection system supplied by KLA- Tencor Corporation of San Jose, California, US. The data from the inspection system is analysed by software

techniques incorporating proprietary (to KLA-Tencor) algorithms in order to identify the defects. Other suitable inspection systems and software known to the skilled person may be used. The die-die comparison described above results in comparison data 45 (also known as PWQ comparison data 45) comprising a plurality of defects. These defects may be identified by coordinates describing the locations of defects in the form of a list. Step 70 is the generation of additional information. In this specific example the additional information is OPC data 75. This step is usually performed before either die is produced (steps 20 and 30) and usually before the reticle is fabricated. Step 70 is part of the design and optimisation process of the IC. Several iterations of OPC optimisation may be carried out before a final IC layout is found. Although OPC optimisation iterations are used to reduce defects in the layout by varying the shapes of features, certain features highlighted by the OPC process as falling outside of acceptable parameters (i.e. likely to result in significantly distorted features on the wafer) may in fact not cause any electrical defect in the resultant device. For instance, the OPC process may identify the shortening of a connection track due to optical distortion. However, if the shortened track does not lead to a broken connection this particular distorted feature will not be considered a real defect and the layout of the IC will not require any correction. The final OPC iteration may- generate many similar acceptably distorted features and this additional information will be in the form of a list of coordinates forming the OPC data set 75.

It is likely that many features identified by the simulated optical effects during the OPC process and forming the OPC distortion data set 45 will also be identified as defects when performing the die-die comparison of step 40. Step 50 compares the OPC distortion data set with the PWQ comparison data set 45 generated from step 40 and step 60 automatically prioritises this data set accordingly and results in defect data 65. For instance, a feature identified as being located at a particular coordinate within the OPC data set 75 and therefore, having distortions that are acceptable corresponding with a feature in the comparison data set 45 at substantially the same location will be considered to be the same feature. This feature will be prioritised as having a low priority and requiring little of no further analysis. Defects within the comparison data set 45 having coordinates that do not correspond with coordinates of features in the OPC data set 75 (additional information) are prioritised as having a high priority, i.e. more analysis will be carried out on these defects.

Defects within the comparison data 45 that have a low priority may be retained within the defect data 65 but assigned a low priority or they may be deleted or filtered out entirely. The automatic prioritisation step 60 may also include assigning defects with a prioritisation falling on a sliding scale of prioritisation values depending on the similarity of the defect to the particular feature of the additional information. For instance, this may be based on the proximity of the coordinates of the defect to those of the feature specified in the OPC data 75.

The automatic prioritisation step 60 may be implemented in a computer program loaded on a computer.

Optionally, a further step 80 may be used to feed back the results of step 60 (defect data 65) to the OPC process 70 in order that the OPC optimisation process can be modified so that fewer real (electrically significant) defects are generated in the wafer die. In this way the OPC optimisation may be fine tuned and optimised so that real defects are eliminated at the design stage. This may be done by comparing the defect data 65 with the OPC data 75.

Once the defect data set 65 is generated each individual defect may be investigated and corrected if necessary. Such an investigation may be carried out by- obtaining a SEM image of the defect. FIG. 2 shows a flow chart describing a method 10' for detecting defects in an integrated circuit according to a second aspect of the present invention. Steps that are identical to those described with reference to FIG. 1 have the same reference numerals and shall not be described again.

The layout of the IC is stored in a library, as shown in step 120. This includes the layout of features forming each component cell or sub-assembly of the IC. For instance a cell may represent an array of memory gates . Each cell may be duplicated many times within the IC layout. Therefore, a defect within a particular cell may be duplicated in each instance of that cell forming the IC device on the wafer die. Furthermore, it is only necessary to correct a defect in the design of the cell as this correction will follow through to each instance of the cell.

The PWQ comparison data 45 will contain defects found in each instance of the particular cell containing it. If a

cell is duplicated on the die many times so will the defect. Furthermore, it is not necessary to investigate each of these duplicated defects under the SEM as each one will be identical . Library data 130 contains information regarding the duplication of cells. Step 110 compares the PWQ comparison data 45 with the library data 130 to identify duplicate defects. Step 60' removes all but one of each repeated defect forming the final defect data set 65. In this way the defect data set 65 may be significantly reduced in size. Steps 120, 110 and 60' may be introduced into method 10 of FIG. 1 so that both false defects and repeated defects are removed from the IC layout.

FIG. 3 illustrates results of the die-die comparison step 40. FIG. 3 shows the layout of features contained within corresponding portions of a pair of dies fabricated according to steps 20 and 30 of methods 10 and 10' shown in FIG. 1 and FIG. 2. Portion 200 shows the layout of features fabricated with the reticle image at optimum focus. Portion 210 shows the layout of features fabricated with the reticle image focused at 0.2 um out of the plane of the wafer. Differences between the dies highlight potential defect sites. Three particular defect sites, 230, 250 and 270 are highlighted on portion 210. These correspond to missing or broken features. The corresponding features at optimum focus, 200, 240 and 260 are highlighted on portion 200, respectively. It is likely that the sites 230, 250 and 270 will lead to electrical failure points in a resultant device . FIG. 4 also illustrates the results of the die-die comparison step 40 and includes the layout of two portions 310, 300 of a pair of dies each fabricated with a reticle

imaged in the plane of the wafer and at 0.2 urn from the plane of the wafer, respectively. Differences in the lengths of connection tracks that should reach the dashed line 320 are highlighted by dashed lines 330. Although there are differences between the features of this pair of dies and the die-die comparison step 40 will identify these differences as defects, these defects will not cause electrical failure points in the resultant device. Such features may be identified during the OPC optimisation process 70 and contained within the additional information (OPC data 75) . Therefore, step 60 should prioritise these defects by assigning them with a low priority within the PWQ comparison data 45 in step 60 of method 10 shown in FIG. 1 resulting in a defect data set 65 comprising defects that require fixing identified as high priority.

Once high priority defects have been identified and any false defects or repeating defects have been assigned a low priority or deleted it may be necessary to investigate the high priority defects in greater detail to determine whether or not the IC layout design requires modification. This is usually carried out by imaging the defects using SEM techniques on a separate instrument to that used to compare the pair of dies. It is usually necessary to physically move the dies to a different instrument such as an SEM and then locate the individual features under the SEM. The particular features may be of the order of 1 um or less in size. It may not be possible to accurately locate the die on an SEM stage to within a tolerance of this order. It is therefore, necessary to provide a method of accurately locating identified defects within the dies.

FIG. 5 shows the schematic layout of three predetermined features or targets 400, 410, 420 incorporated

into the reticle and used as reference points to accurately locate the resultant die on an SEM stage. The targets 400, 410, 420 are deliberately formed so that they will be identified as defects during the die-die comparison stage 40 as their structure changes significantly as the focus of the reticle changes between dies.

Furthermore, the targets may be chosen to make it easier to locate within an SEM instrument. Obviously, these targets are not defects but are deliberately introduced into the IC layout.

FIG. 5 shows portions of two dies fabricated with a reticle forming an image at different focus planes relative to the wafer. Portion 460 is formed with a reticle image in focus in the plane of the wafer and so the predetermined features or targets 400, 410, 420 are undistorted. Portion 470 is formed with the reticle image out of focus with respect to the wafer. The three targets 400', 410', 420' are therefore, distorted. In particular, the central regions 430, 440, 450 of each target shows the highest distortion. The sharp points at the centre 430, 450 of targets 400 and 420 correspond with a less sharp waist of targets 400' and 420', respectively. The square feature at the centre 440 of target 410 corresponds with an enlarged square and the centre 440 of target 410'. The targets will therefore, be identified as defects within the die-die comparison step 40.

The actual location of each target on the IC design will be known from the design of the device. The coordinate of each target may also be found from the die-die comparison stage. This provides a correlation between the coordinate system used in the die-die comparison and the coordinate

system used during IC design and so each coordinate system may be calibrated against each other.

Furthermore, the targets 400, 410, 420 may be used to locate real defects within the SEM instrument. Once a target has been located within the SEM instrument its coordinate within the defect data 65 may be looked up. The location of any defect may then be located more accurately also from its coordinate in the defect data 65 using the target coordinate as a fixed and known reference point. Although it is possible to use this calibration method with a single target, several targets at different locations may be used to improve accuracy. For instance, a target at two or more corners of the die may be used. This will avoid location errors due to rotation of the die. The targets may be located within the features that have electrical functions in the resultant device or outside of the region of electrical function. Locating the targets outside of the active region of the device has the advantage that space is not wasted within the device. As will be appreciated by the skilled person, details of the above embodiment may be varied without departing from the scope of the present invention, as defined by the appended claims .

For example, the displacement between the focal planes used to produce a pair of dies may be a value dependent on the critical dimension (CD) of the integrated circuit. As the CD decreases so will the displacement of the focal planes. For instance a displacement of 0.1 urn or 0.05 urn may be used. However, if no defects are found from pairs of dies produced using a particular displacement of focal planes a larger (courser) displacement may be used such as 0.2 urn to 0.5 um or 0.2 urn to 1 urn.

For all embodiments described above further prioritisation of the defect data set 65 may be performed. This prioritisation may be based on prioritisation parameters such as detectability, impact and design for manufacturing (DFM) prioritisation guidelines. Also yield, risk information and computer aided design (CAD) analysis may be used to prioritise the defects. The highest priority defects may be analysed and reviewed first.

Parameters other than focus displacement may be varied in order to fabricate the first and second die. For example, exposure energy (dose level) , die focus levelling, or illumination source shape. Alternatively, the parameter may be separate reticles each produced to different specifications and each die may then be fabricated using one of the two separate reticles.

The optional step 80 may feedback to the OPC process the comparison data 45 before it has been prioritised or feedback the defect data 65 after prioritisation. Therefore, instead of comparing the defect data 65 with the OPC data 75, as an alternative the comparison data 45 may be compared with the OPC data 75.

Other simulation tools other than OPC optimisation may be used to analyse the design layout and generate additional information to be used in conjunction with the comparison data 45 to prioritise the defects. Such tools may include design rule check (DRC) software or layout density analysis software ..

Other suitably shaped targets may also be used. For instance, concentric circles or polygons may be used. The technique of using targets to assist with the location of defects may be used in combination with the method 10 described with reference to FIG. 1 or with the

method 10' described with reference to FIG. 2. Furthermore, this technique may also be used with a combination of methods 10 and 10'.

It will also be appreciated that instead of the deliberate introduction of a dedicated target into the design one or more defects may be used in the place of these targets. For instance, features highlighted by the OPC optimisation process as likely to be optically distorted in the resultant die but that do not require fixing (because they will not cause electrical faults) will have known locations in the design and on the die following the OPC optimisation process. These features should also be identified in the die-die comparison step 40. Therefore, these features may be used as reference points to locate defects that require SEM investigation. Obviously, such reference defects should not be removed during the prioritisation step 60, 60'.

A simplified method for using the predetermined feature to align the position of one of the dies may comprise aligning the predetermined feature to a particular point in the SEM instrument.