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Title:
METHOD AND DEVICE FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT HIERARCHY
Document Type and Number:
WIPO Patent Application WO/2008/004346
Kind Code:
A1
Abstract:
A semiconductor integrated circuit hierarchy designing device (1) includes: hierarchical block arrangement means (1-02) for arranging a hierarchical block set on a chip; hierarchical block terminal arrangement means (1-03) for performing hierarchical block terminal arrangement so that coordinates of the hierarchical block set having the same function coincide with coordinates of the same hierarchical block terminal; in-hierarchical block layout means (1-06) for performing layout design in hierarchical blocks of respective types; and chip layout assembling means (1-07) for completing the entire chip layout design by copying the obtained layout pattern.

Inventors:
OKAMOTO TAKUMI (JP)
Application Number:
PCT/JP2007/000735
Publication Date:
January 10, 2008
Filing Date:
July 05, 2007
Export Citation:
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Assignee:
NEC CORP (JP)
OKAMOTO TAKUMI (JP)
International Classes:
H01L21/82; G06F17/50
Foreign References:
JPH0887899A1996-04-02
JPH03129754A1991-06-03
JPH03154363A1991-07-02
Attorney, Agent or Firm:
HAYAMI, Shinji (2-17-16 Ebisu-Nish, Shibuya-ku Tokyo 21, JP)
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