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Title:
METHOD AND DEVICE FOR GENERATING ERROR DETECTING REDUNDANT BIT
Document Type and Number:
WIPO Patent Application WO/2019/030860
Kind Code:
A1
Abstract:
[Purpose] To provide a novel method and device with which a decrease in detection accuracy and a considerable increase in calculation amounts can be avoided, and with which a redundant bit allowing for error detection can be generated using part of information bits. [Solution] A redundant bit generation device for generating a redundant bit which is added to blocked information bits and allows for error detection has: a CRC calculation function (30) for generating a predetermined number (r) of redundant bits from information bits, using a CRC polynomial (32); and a bit interchange function (31) for distributing the predetermined number of redundant bits among the information bits, using a replacement pattern (33) established in accordance with the CRC polynomial (32).

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Inventors:
KAMIYA NORIFUMI (JP)
CHAKI PRAKASH (JP)
Application Number:
PCT/JP2017/028942
Publication Date:
February 14, 2019
Filing Date:
August 09, 2017
Export Citation:
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Assignee:
NEC CORP (JP)
International Classes:
H03M13/09; H03M13/13; H04L1/00
Foreign References:
US20160079999A12016-03-17
JP2000201085A2000-07-18
Other References:
NTT DOCOMO: "Distributed simple parity check Polar codes", 3GPP R1-1705757, 7 April 2017 (2017-04-07), XP051243872
Attorney, Agent or Firm:
KATSURAGI Yuji (JP)
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