Title:
METHOD AND DEVICE FOR HIGH-SPEED CACHE COLLISION HANDLING
Document Type and Number:
WIPO Patent Application WO/2021/237424
Kind Code:
A1
Abstract:
A method and device for high-speed cache collision handling, related to the technical field of chips. The method comprises: acquiring collision information of a high-speed cache (S401); determining, on the basis of the collision information, a second cache line satisfying a preset criterion among multiple first cache lines (S402), the second cache line being a cache line having a higher frequency of occurrence of high-speed cache collisions; and relocating a stored object at a first virtual address in a memory corresponding to the second cache line from the first virtual address to a second virtual address in the memory corresponding to a third cache line in a high-speed cache (140), the third cache line being a cache line having a lower frequency of occurrence of high-speed cache collisions. The method reduces high-speed cache misses incurred by high-speed cache collisions, and optimizes the front-end performance of a CPU, thus acquiring the benefits of excellent performance and power consumption of the CPU in actual operating scenarios.
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Inventors:
LI PENG (CN)
ZHANG MI (CN)
LIN WEI (CN)
ZHANG MI (CN)
LIN WEI (CN)
Application Number:
PCT/CN2020/092167
Publication Date:
December 02, 2021
Filing Date:
May 25, 2020
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F9/38
Foreign References:
| CN107479860A | 2017-12-15 | |||
| CN110716887A | 2020-01-21 | |||
| US20190004968A1 | 2019-01-03 | |||
| US20190121748A1 | 2019-04-25 |
Attorney, Agent or Firm:
BEIJING ZBSD PATENT&TRADEMARK AGENT LTD. (CN)
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