[0001] Topological quantum computing is based on the phenomenon whereby non-abelian anyons, in the form of "Majorana zero modes" (MZMs), can be formed in regions where a semiconductor is coupled to a superconductor. A non-abelian anyon is a type of quasiparticle, meaning not a particle per se, but an excitation in an electron liquid that behaves at least partially like a particle. MZMs are a particular bound state of such quasiparticles.

[0002] Under certain conditions, MZMs can be formed close to an interface between a semiconductor and superconductor. For example, MZMs may be formed in a device comprising a semiconductor nanowire coated with a superconductor. A nanowire has a length which is many times greater than its diameter and can be considered as a 1- dimensional system. MZMs can also be formed in two-dimensional systems, comprising a superconductor coupled to a quantum well hosting a 2-dimensional electron gas, such as described by Suominen et al, Phys. Rev. Lett. 119, 176805 (2017) and Nichele et al, Phys. Rev. Lett. 119, 136803 (2017).

[0003] When MZMs are induced in a structure, the structure is said to be in the "topological regime". To induce this requires a magnetic field, conventionally applied externally, and also cooling of the structure to a temperature that induces superconducting behaviour in the superconductor material.

[0004] Topological devices are useful for creating a quantum bit which can be manipulated for the purpose of quantum computing. A quantum bit, also referred to as a qubit, is an element upon which a measurement with two possible outcomes can be performed, but which at any given time (when not being measured) can in fact be in a quantum superposition of the two states corresponding to the different outcomes.

[0005] To induce MZMs, the device is cooled to a temperature where the superconductor (e.g. aluminium) exhibits superconducting behaviour. The superconductor causes a proximity effect in the adjacent semiconductor, whereby a region of the semiconductor near the interface with the superconductor also exhibits superconducting properties. Le. a topological phase behaviour is induced in the adjacent semiconductor as well as the superconductor. It is in this region of the semiconductor where the MZMs are formed.

[0006] Another condition for inducing the topological phase where MZMs can form is the application of a magnetic field in order to lift the spin degeneracy in the semiconductor. Degeneracy in the context of a quantum system refers to the case where different quantum states have the same energy level. Lifting the degeneracy means causing such states to adopt different energy levels. Spin degeneracy refers to the case where different spin states have the same energy level. Spin degeneracy can be lifted by means of a magnetic field, causing an energy level spilt between the differently spin-polarized electrons. This is known as the Zeeman effect. Typically, the magnetic field is applied by an external electromagnet.

[0007] The behaviour of semiconductor-superconductor hybrid devices is dependent upon the quality of the materials used, and the quality of the interfaces between those materials. There is a need for fabrication processes which can allow these requirements to be met.

[0008] One approach to fabrication is so-called in situ fabrication. In an in situ process, the semiconductor and superconductor components are all fabricated in the same apparatus while maintaining a very high vacuum. The device is not removed from the apparatus, nor is it exposed to the atmosphere.

[0009] Although in situ fabrication may allow high-quality devices to be obtained, the requirement to maintain a very high vacuum throughout the process is a significant constraint. Existing processes have limitations on scalability, yield, throughput, and reproducibility.

Summary

[0010] In one aspect there is provided a method of fabricating a semiconductor device. The method includes providing a workpiece comprising a semiconductor structure, the semiconductor structure comprising a substrate and a semiconductor component arranged on a surface of the substrate; a capping layer over the semiconductor structure; and a shadow wall comprising a leg and a body connected to the leg. The capping layer is a layer of arsenic or antimony. The leg of the shadow wall extends from the semiconductor structure through an aperture in the capping layer. The body of the shadow wall is on the capping layer and over the semiconductor structure. The method further comprises removing the capping layer; and, after removing the capping layer, depositing a further material onto a first region of the semiconductor structure. The shadow wall prevents deposition of the further material onto a second region of the semiconductor structure.

[0011] The capping layer protects the surface of the semiconductor component, and can be removed without degrading the quality of the surface of the semiconductor component. This allows the further material to be deposited in an environment which is different from that in which the semiconductor structure is fabricated, while allowing a pristine interface between the semiconductor component and the further material to be obtained.

[0012] Another aspect provides a workpiece useful in the method. The workpiece comprises a semiconductor structure, the semiconductor structure comprising a substrate and a semiconductor component arranged on a surface of the substrate; a capping layer over the semiconductor structure; and a shadow wall comprising a leg and a body connected to the leg. The capping layer is a layer of arsenic or antimony. The leg of the shadow wall extends from the semiconductor structure through an aperture in the capping layer. The body of the shadow wall is on the capping layer and over the semiconductor structure.

[0013] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Nor is the claimed subject matter limited to implementations that solve any or all of the disadvantages noted herein. Brief of the

[0014] To assist understanding of embodiments of the present disclosure and to show how such embodiments may be put into effect, reference is made, by way of example only, to the accompanying drawings in which:

Fig. 1 is a flow diagram outlining an example method of fabricating a semiconductor device;

Figs. 2A to 2E are schematic cross-sections of workpieces obtained at various stages of the method of Fig. 1;

Fig. 3 is a schematic perspective view of an example shadow wall;

Fig. 4 is a schematic plan view of an example shadow wall;

Fig. 5 is an annotated scanning electron microscopy image of a first example workpiece; and

Fig. 6 is a scanning electron microscopy image of a second example workpiece.

Detailed Description of Embodiments

[0015] Directional terms such as "top", "bottom", "left", "right", "above", "below", "horizontal" and "vertical" are used herein for convenience of description, and refer to the orientation shown in the drawings. For the avoidance of any doubt, this terminology is not intended to limit the orientation of the device in an external frame of reference.

[0016] A first component which is "on" a second component is in direct contact with the second component. A first component which is "over" a second component may be directly on the second component, or spaced from the second component by one or more other components.

[0017] A "workpiece" is an intermediate product obtained during fabrication of a semiconductor device. [0018] A high vacuum is an environment having a gas pressure of less than or equal to 100 mPa. An ultra-high vacuum is an environment having a gas pressure of less than or equal to 100 nPa.

[0019] As used herein, the term "superconductor" refers to a material which is capable of superconductivity when cooled to a temperature below a critical temperature, T _c , of the material.

[0020] The surface of a semiconductor may be described as pristine when it is in an "as- grown" state, substantially free of native oxides and other contaminants. When a metal is grown on a pristine surface of a semiconductor, the interface between the metal and the semiconductor may be described as pristine.

[0021] Described herein are methods of fabricating semiconductor devices, such as semiconductor-superconductor hybrid devices, using a combination of a removable capping layer and shadowing structures.

[0022] The methods provided herein may allow the surface of the semiconductor to be kept pristine. This may allow a high-quality semiconductor-superconductor interface to be obtained. The performance of a topological qubit based on a semiconductor-superconductor hybrid structure is highly dependent upon the quality of the interface.

[0023] In the methods, a semiconductor structure is prepared by growing a semiconductor component on a substrate. The growth typically takes place before any shadowing structures are formed on the substrate. The presence of shadowing structures during growth of a semiconductor component is not desirable. Shadowing structures hinder the diffusion of adatoms over the surface of the substrate. This makes it more difficult to obtain a flat, uniform film of semiconductor. The presence of shadowing structures during growth of the semiconductor may therefore reduce the quality and/or homogeneity of the semiconductor. Semiconductor materials which are grown at low temperature and/or from precursors with low diffusion coefficients are affected particularly badly by the present of shadow walls. [0024] Shadowing structures may also impose other constraints on semiconductor growth, such as a limitation on the maximum thickness of the semiconductor component.

[0025] After preparing the semiconductor structure, the semiconductor structure is then capped with a layer of arsenic or antimony. Such capping layers may be applied to most surfaces. The capping layer allow the structure to be transferred between tools that do not share the same vacuum environment. This may allow the best available tools and materials to be used without the limitations associated with established in situ approaches: providing certain combinations of tools under the same vacuum environment may not always be possible.

[0026] Shadowing structures are then formed by a lithographic process. Lithographic processes may allow very high resolution, scalability, throughput, reproducibility and alignment, as well as high level of flexibility.

[0027] After forming the shadowing structures, the semiconductor structure may be loaded into a high-vacuum chamber. The capping layer may then be removed in a high vacuum environment.

[0028] Next, the shadowing structures are used to create desired patterns of a further material on the pristine surface of the semiconductor structure. A flow of material is directed toward the semiconductor structure. The shadowing structures block the flow, thereby defining shadowed regions which do not receive the material. Material is deposited in a controlled manner onto regions which are not shadowed.

[0029] The use of shadowing structures allows the further material to be patterned without the needed for destructive processes such as etching which could impact the performance of the device.

[0030] An example method of fabricating a semiconductor device will now be explained with reference to Figs. 1 and 2A to 2E. Fig. 1 is a flow diagram outlining the method, and Figs. 2A to 2E illustrate workpieces obtained at various stages of the method. [0031] At block 101, a workpiece is provided. An example workpiece 200 is illustrated in Fig. 2C. The workpiece includes a semiconductor structure 210, comprising a substrate 212 and a semiconductor component 214 arranged on the substrate 212. A capping layer 220 covers the surface of the semiconductor structure 210. The capping layer is a layer of arsenic or antimony. The workpiece further includes a shadow wall 230. The shadow wall of this example has two legs, which extend from respective trenches in the semiconductor structure 210 and through respective apertures in the capping layer. The shadow wall 230 further includes a body extending between the legs. The body is spaced from the semiconductor structure 210 by the capping layer 220.

[0032] The substrate 212 provides a base on which the semiconductor component may be grown. The nature of the substrate is not particularly limited, and may be selected as appropriate depending upon the nature of the semiconductor component to be formed. The substrate 212 typically comprises a wafer, i.e. a piece of single crystalline material. The substrate 212 may comprise a lll-V semiconductor material, such as indium phosphide, indium antimonide, indium arsenide, or gallium arsenide. Other wafer materials, such as silicon, may be used.

[0033] The semiconductor component 214 may comprise a semiconductor heterostructure, for example a semiconductor heterostructure for hosting a two-dimensional electron gas or a two-dimensional hole gas.

[0034] An example semiconductor heterostructure comprises a lower barrier arranged epitaxially on the substrate; a quantum well arranged epitaxially on the lower barrier; and an upper barrier layer arranged epitaxially on the quantum well. The quantum well comprises a material which is different from the material(s) of the lower barrier and upper barrier. The materials of the lower barrier layer and the upper barrier layer may each be independently selected.

[0035] The quantum well may comprise a layer of semiconductor material which has a relatively small band gap compared to the materials of the upper and lower barriers. Illustrative materials useful for forming quantum wells are described in, for exam pie, Odoh and Njapba, "A Review of Semiconductor Quantum Well Devices", Advances in Physics Theories and Applications, vol. 46, 2015, pp. 26-32; and S. Kasap, P. Capper (Eds.), "Springer Handbook of Electronic and Photonic Materials", DOI 10.1007/978-3-319-48933-9_40.

[0036] The quantum well is typically a few atomic layers thick. For example, the quantum well may have a thickness in the range 2 to 7 nm. The configuration of the upper and lower barriers is not particularly limited provided that a 2-dimensional electron gas ("2DEG") or a 2- dimensional hole gas ("2DHG") can be formed in the quantum well layer. The lower barrier may comprise one or more layers of one or more different materials. The upper barrier may comprise one or more layers of one or more different materials. Constructing a barrier from a plurality of layers may provide defect filtering, i.e. may reduce the effects of dislocations in the crystalline structure of the materials used.

[0037] The semiconductor component may be fabricated by selective area growth. In such implementations, a dielectric mask used in the selective area growth may remain in the semiconductor structure.

[0038] The semiconductor material(s) used to form the semiconductor component are not particularly limited. The semiconductor component may for example comprise one or more lll-V semiconductors, in particular a compound or allow comprising at least one group III element selected from indium, aluminium and gallium; and at least one group V element selected from arsenic, phosphorous, and antimony.

[0039] The lll-V semiconductor material may include at least one of arsenic and antimony. In such implementations, fabrication of the semiconductor component and formation of the capping layer may both make use of the same source of arsenic or antimony. [0040] The 111 -V semiconductor material may, for example, be a material of Formula 1: InAsxSbi-x (Formula 1) where x is in the range 0 to 1. In other words, the semiconductor component may comprise indium antimonide (x=0), indium arsenide (x=l), or a ternary mixture comprising 50 % indium on a molar basis and variable proportions of arsenic and antimony (0 <x <1).

[0041] Another class of materials useful as the semiconductor component are ll-VI semiconductor materials. Examples of ll-VI semiconductor materials include cadmium telluride, mercury telluride, lead telluride and tin telluride.

[0042] A capping layer 220 covers the semiconductor structure 210. The capping layer is a barrier which protects the semiconductor component 214 from its external environment. For example, if workpiece 200 is exposed to the atmosphere, capping layer 220 may protect the semiconductor component 214 from oxidation.

[0043] The capping layer 220 is a layer of arsenic or antimony. The capping layer may be an amorphous layer of arsenic or antimony.

[0044] The capping layer 220 will be removed at a later stage of the process, to allow deposition of a further material onto the semiconductor structure. Arsenic and antimony sublime when heated to a moderate temperature (e.g, a temperature of less than or equal to about 350 °C) in a high vacuum. It has been found that arsenic and antimony capping layers are effective for protecting pristine semiconductor surfaces, and are removable without degrading the surface of the semiconductor.

[0045] Arsenic has a lower sublimation temperature than antimony. Some semiconductor materials are temperature-sensitive, and minimising heating may be desirable in some implementations.

[0046] A shadow wall 230, also referred to as a shadowing structure, is partially embedded in the capping layer 220. The example shadow wall 230 has legs which extend through the capping layer 220 into trenches in the semiconductor structure. The shadow wall further has a body extending between the legs. The body rests on top of the capping layer 220. When the capping layer 220 is removed, the body overhangs the semiconductor structure with the legs providing mechanical support for the body.

[0047] The shadow wall 230 will be used later, after removal of the capping layer 220, to control deposition of a material onto the semiconductor structure 210. In use, the shadow wall 230 acts as a mask or stencil: the shadow wall 230 shields a region of the semiconductor structure 210 by blocking a flow of the material such that material is not deposited in the shielded region. The shielded region may be referred to as a shadow region.

[0048] The use of shadow walls may allow for non-destructive patterning of materials. In other words, materials may be deposited in a controlled manner without the need to remove excess material by chemical or physical methods. Removal of excess material, for example by etching, can damage the semiconductor structure.

[0049] Blocks 101A to 101E of Fig. 1 illustrate an example method for preparing workpiece 200.

[0050] Preparing the workpiece proceeds in two phases. In a first phase comprising blocks 101A and 101B, a workpiece comprising a semiconductor structure and a capping layer as illustrated in Fig. 2A is prepared. Subsequently, in a second phase comprising blocks 101C to 101E, a shadow wall is formed yielding a workpiece 200 as illustrated in Fig. 2C.

[0051] At block 101A of the first phase of the method, a semiconductor structure 210 comprising a semiconductor component 214 arranged on a surface of a substrate 212 is prepared.

[0052] The semiconductor component 214 is typically grown epitaxially on the surface of the substrate 210. Growing the semiconductor component may comprise performing molecular beam epitaxy, a chemical vapour deposition process such as metalorganic vapour phase epitaxy ("MOVPE"), or the like. [0053] In some implementations, the semiconductor component may be grown by selective area growth ("SAG"). SAG makes use of a mask to control the growth, such that semiconductor grows at selected locations. For example, SAG may be used to grow semiconductor nanowires, or a network of such nanowires. Where SAG is used, the mask may remain in the finished device. In such implementations, the mask is considered part of the semiconductor structure 210.

[0054] The semiconductor component may comprise a single material, or multiple materials. Where the semiconductor component comprises more than one material, more than one growth technique and/or more than one set of growth conditions may be used.

[0055] In the present example, the semiconductor component 214 is grown before shadow wall 230 is formed. Growing the semiconductor component in the absence of shadow walls may allow the growth conditions for the semiconductor component to be optimized freely. Growing the semiconductor component in the absence of shadow walls may allow a wider range of semiconductor component configurations. For example, the thickness of the semiconductor component may be freely varied.

[0056] Semiconductor components may be grown in the presence of shadow walls, however this may impose additional constraints on growth conditions and/or the configuration of the semiconductor components. Growing semiconductor components in the presence of shadow walls may impose an upper limit on the thickness of the semiconductor component. Shadow walls may interfere with semiconductor growth by limiting adatom diffusion across the surface of the substrate.

[0057] The operations of block 101A are typically performed in an ultra-high vacuum.

[0058] At block 101B, after preparing the semiconductor structure 210, a capping layer 220 is deposited over the semiconductor structure 210. This yields a workpiece of the type illustrated in Fig. 2A. [0059] The capping layer 220 serves to protect the semiconductor structure 210 during subsequent processing steps. In particular, the capping layer 220 protects the surface of semiconductor component 214. In addition, during formation of a shadow wall in phase 2 of the method, the thickness of the capping layer 220 will determine the spacing between body of the shadow wall and the top surface of the semiconductor structure.

[0060] The capping layer 220 is a layer of arsenic or antimony. The arsenic or antimony is typically in an amorphous form.

[0061] The capping layer 220 may be deposited at a low temperature in an ultra-high vacuum, for example at temperatures of less than or equal to 70°C, optionally less than or equal to 30°C. Maintaining the workpiece at a low temperature may be desirable in implementations where the semiconductor structure is temperature-sensitive.

[0062] The arsenic or antimony may be supplied as elemental arsenic or antimony; or in the form of an appropriate precursor which undergoes a reaction in situ to produce arsenic or antimony. An example precursor for arsenic is arsine. When the semiconductor component 214 comprises a material which includes arsenic or antimony, the arsenic or antimony source used in the growth of the semiconductor component may conveniently be used to deposit the capping layer.

[0063] The thickness of the capping layer 220 may be readily controlled, and may be selected as appropriate based on the desired spacing between the shadow wall and the semiconductor structure. The capping layer may have a thickness of at least 15 nm, optionally at least 20 nm, as this may allow a smooth capping layer to be obtained reliably.

[0064] The operations of the first phase may be performed while maintaining the workpiece under vacuum, e.g. a high vacuum or ultra-high vacuum. The workpiece is not removed from the vacuum until after block 101B is completed. This may maintain a pristine surface of the semiconductor component. A pristine surface is an "as-grown" surface, substantially free of native oxides and contaminants. [0065] For example, the operations of blocks 101A and 101B may both be performed in a semiconductor growth chamber. Alternatively, blocks 101A and 101B may be performed in respective different chambers if the chambers are coupled such that the workpiece can be transferred between the chambers without exposure to the open atmosphere. An apparatus comprising two or more vacuum chambers which are coupled in this way may be referred to as a cluster tool.

[0066] After completing the first phase, the method moves to a second phase, in which a shadow wall 230 is formed on the workpiece. The second phase comprises the operations of blocks 101C, 101D, and 101E of Fig. 1.

[0067] Throughout the second phase, the semiconductor component 214 is protected by capping layer 220. The workpiece may therefore be exposed to a wide range of processing conditions without damaging the surface of the semiconductor component 214. In particular, the capping layer 220 may protect the surface of the semiconductor component 214 from oxidation.

[0068] At block 101C, one or more apertures 222a, 222b in the capping layer 220 are formed. In the present example, the apertures are formed by etching the capping layer 220.

[0069] The apertures expose regions of the semiconductor structure 210. The legs of the shadow wall 230 will be affixed to the semiconductor structure in the exposed regions. The remainder of the semiconductor structure 210 remains protected by the capping layer 220.

[0070] The apertures may extend into semiconductor structure 210, as illustrated in Fig. 2B. In other words, the etch may further comprise etching trenches in the semiconductor structure. Providing such trenches may allow the shadow wall to be affixed more robustly to the semiconductor structure.

[0071] Where trenches are present, the trenches may be shallow and may have a depth of the order of a few nanometres, e.g. in the range 1 to 10 nm. It has been found that shallow trenches provide good adhesion. Typically, it is desirable to minimize the extent of the etch in order to maximize the quality of the semiconductor component.

[0072] The etch may be controlled by a mask. The mask may be formed by a lithographic process, such as electron beam lithography.

[0073] The conditions used for the etch are not particularly limited. The etching may be a plasma dry etch, or may be a wet etch.

[0074] It may be desirable for the regions of the semiconductor structure exposed by the etch to be as small as possible, and/or spaced as far as possible from regions of the semiconductor structure which will be used actively in the finished device. This may further help to prevent damage to the active regions of the semiconductor structure.

[0075] As an alternative to lithography and etching, the apertures in the capping layer may be formed by heating selected portions of the capping layer. For example, the apertures may be formed by laser ablation or the like.

[0076] Phase 2 continues with block 101D, in which a resist is applied overthe semiconductor structure 210. The resist fills the apertures 222a, 222b formed in block 101C, and covers the top surface of the capping layer 230. Applying the resist may comprise spin-coating the semiconductor structure with a resist composition. The thickness of the resist will determine the thickness of the body of the shadow wall.

[0077] The nature of the resist is not particularly limited provided that, following exposure and development, a shadow wall which is compatible with the deposition process used later at block 103 is obtained.

[0078] For example, the resist may comprise hydrogen silsesquioxane, HSQ. Liquid compositions comprising HSQ are commercially available, and may be applied by spincoating. HSQ is a negative electron beam resist which, upon exposure, is converted into a silicon oxide, SiO _x . Silicon oxides have good compatibility with a range of deposition processes, including molecular beam epitaxy. Usefully, silicon oxides do not degas under the conditions used for molecular beam epitaxy.

[0079] More generally, inorganic negative electron beam resists may be used. Carbon can act as a dopant of semiconductor materials, and avoiding the use of resists containing carbon is therefore preferable in many implementations.

[0080] The resist is selectively exposed and developed at block 101E, to form a shadow wall 230 having legs at positions corresponding to the apertures 222a, 222b in the capping layer 220 and a body supported by the capping layer 220. Fig. 2C illustrates an example workpiece obtainable at this stage.

[0081] The conditions of the exposure and development may be selected as appropriate based on the nature of the resist chosen. For example, HSQ may be exposed using an electron beam, and developed using tetramethyl ammonium hydroxide, TMAH.

[0082] The exposure and development define the shape of the shadow wall 230. Resist in the apertures 222a, 222b is developed to form legs of the shadow wall. Regions of the resist on the surface of the capping layer are developed to form the body of the shadow wall.

[0083] By controlling which regions of the resist are exposed, there is significant freedom to control the configuration of the finished shadow wall. Some example shadow walls will be discussed in more detail below, with reference to Figs. 3 to 6.

[0084] Optionally, if desired, more than one layer of resist may be applied, selectively exposed, and developed. This may allow shadow walls with more elaborate shapes to be obtained.

[0085] After forming the shadow walls, the method proceeds to phase 3. Phase 3 comprises removing the capping layer at block 102, and depositing one or more portions of one or more further materials over the semiconductor structure at block 103. [0086] Phase 3 of the method may be performed while maintaining the workpiece under a vacuum, typically a high vacuum or ultra-high vacuum. For example, phase 3 may be performed in a molecular beam epitaxy apparatus.

[0087] In implementations where a mask is used to control the formation of the apertures in the capping layer, the mask is removed before transferring the workpiece to the vacuum. The mask may be removed before applying the resist at block 101D, or after forming the shadow wall at block 101E.

[0088] At block 102, the capping layer 230 is removed. Removing the capping layer exposes the semiconductor structure 210, as illustrated in Fig. 2D.

[0089] Removing the capping layer may comprise heating the capping layer under vacuum to sublime the arsenic or antimony. For example, the capping layer 230 may be heated to a temperature in the range 250 to 350°C in an ultra-high vacuum. As will be appreciated, the temperature may be varied as appropriate depending on the pressure environment.

[0090] It has been found that capping a semiconductor structure with arsenic or antimony and subsequently removing the arsenic or antimony by heating under vacuum maintains the surface of the semiconductor structure in a pristine condition.

[0091] After removing the capping layer, at block 103, a layer of a further material 240 is deposited onto the semiconductor structure 210 to obtain a workpiece of the type shown in Fig. 2E.

[0092] The nature of the further material is not particularly limited. Non-limiting examples of further materials which may be deposited include metals, dielectrics, and ferromagnetic insulators.

[0093] The further material may comprise a metal. The metal may be a superconductor. The superconductor may be an s-wave superconductor. Examples include aluminium, indium, tin, and lead, with aluminium being preferred in some contexts. [0094] Examples of dielectrics include silicon oxides, SiOx; silicon nitrites, Sil\k; aluminium oxides, AIOx; and hafnium oxides, HfOx.

[0095] Examples of ferromagnetic insulators include EuS, EuO, GdN, YsFesOiz, BisFesOiz, YFeOg, Fe?O3, FesC , SrzCrReOe, CrBrs/Crh, and YTiOs.

[0096] Two or more further materials may be deposited. By way of illustration, block 103 may comprise depositing a metal and then depositing a dielectric.

[0097] To deposit a material, a flow of material 242 is directed toward the semiconductor structure 210. For example, the deposition may comprise molecular beam epitaxy.

[0098] The material is deposited on regions of the semiconductor structure 210 which are not shielded from the flow of material 242 by shadow wall 230. Shadowed regions do not receive the material.

[0099] The configuration of the shadowed regions determined by the shape of shadow wall 230 and the direction of flow 242.

[0100] Fig. 2E illustrates so-called "0-angle deposition", also referred to as line-of-sight deposition. In 0-angle deposition, the direction of flow of the material is perpendicular to the surface of the substrate. In 0-angle deposition, the shadowed regions lie directly under the body of the shadow wall. 0-angle deposition may provide shadows with sharply defined edges, or in other words, a high-resolution deposition.

[0101] Since the deposition of the further material(s) may be controlled precisely using the shadow walls, there is no need to perform any etch to pattern the further materials. By avoiding etching, the surface of the semiconductor component may be maintained in a pristine state.

[0102] Various modifications may be made to the described method. [0103] The method may further comprise one or more additional operations. For example, after block 103, a further capping layer may be applied over the workpiece. The further capping layer may be a layer of arsenic or antimony. In such implementations, phases 2 and 3 of the method may be repeated to allowed patterned deposition of further materials. Alternatively, the capping layer may comprise a dielectric such as a hafnium oxide, for protecting the device.

[0104] Another example of an additional operation is adding gate electrodes. The shadow walls may be used to control deposition of the gate electrodes.

[0105] Still another example of an additional operation comprises forming a component on the shadow wall by depositing material onto the shadow wall. The component may comprise a gate electrode. The material deposited onto the shadow wall may comprise one or more metal layers and/or one or more dielectric layers. In some implementations, a gate structure supported by a shadow wall may be referred to as a frame gate.

[0106] The shadow wall may optionally be removed after the deposition of the further material(s).

[0107] For ease of illustration, the example shows the formation of a single shadow wall, and deposition of one layer of one further material. As will be appreciated, a plurality of shadow walls may be formed, and two or more layers of any number of different further materials may be deposited.

[0108] Fig. 3 is a schematic perspective view of an example shadow wall 300 arranged on a surface 310. Surface 310 may be the top surface of a semiconductor structure, such as semiconductor structure 210 of Figs. 2A to 2E.

[0109] Shadow wall 300 includes legs 332, 334 extending from the surface 310. A body 336 bridges the legs 332, 334 and is spaced from the surface 310 by a distance d3. Distance d3 is determined by the thickness of the capping layer present during fabrication of the shadow wall in phase 2 of the method of Fig. 1. Distance d3 is desirably small, e.g. 20 to 50 nm. A small spacing between the body 336 and the surface 310 may improve the resolution of the deposition, particularly when the shadow wall is used to control a 0-angle deposition process.

[0110] The shape, positions and dimensions dl, d2 of the legs may be controlled by varying the configuration of the apertures formed in block 101C of Fig. 1. The thickness d4 of the body 336 may be controlled by varying the thickness of the resist applied at block 101D of Fig. 1. The shape and dimensions d5, d6 of the body 336 may be controlled by selective exposure of the resist, at block 101E of Fig. 1.

[0111] In implementations where the shadow wall is formed after fabricating the semiconductor structure, constraints on the configuration of the shadow wall may be lifted, since there is no requirement for the shadow wall to be compatible with semiconductor growth conditions.

[0112] In use, when a flow of material is directed toward the semiconductor structure 310 from a direction perpendicular to the surface of the semiconductor structure 310, the shadow wall 300 shadows a region 310a which is directly below the body 336. As will be appreciated, differently shaped shadows would be obtained if the material were applied from a different direction.

[0113] Fig. 4 shows a schematic plan view of the body of a second example shadow wall 400. The illustrated shadow wall 400 has a generally rectangular outer perimeter 410. Legs for supporting the shadow wall would be arranged at or proximate to the outer perimeter 410.

[0114] An aperture 420 in the shape of an elongate slot is arranged toward the middle of body of the shadow wall 400. In use, superconductor material is deposited through the aperture 420 to form a strip of superconductor in the form of a nanowire on an underlying semiconductor structure.

[0115] The aperture 420 is spaced from the perimeter 410 by a distance s. By spacing the aperture from the location of the legs, it may be made possible to deposit material far away from etched regions of the semiconductor structure, and which are therefore the least likely to be damaged during fabrication of the device.

[0116] Fig. 5 shows a scanning electron microscopy image of a shadow wall of the type shown in Fig. 4. As may be seen, an aperture 510 for allowing deposition of a nanowire is provided in the body 500 of the shadow wall. To increase further the distance between the aperture and the legs, the legs are arranged on protrusions at the perimeter of the body.

[0117] An SEM image of a set of shadow walls is shown in Fig. 6. The illustrated shadow walls are configured to separate various electrodes and transmission lines of a semiconductorsuperconductor hybrid device. The figure illustrates that complex shadow wall shapes may be readily achieved using the present methods. Since the shape of the shadow wall is defined lithographically, there is significant freedom to modify the configuration of the shadow walls depending on the nature of the desired device.

[0118] Although the examples described herein relate in particular to semiconductorsuperconductor hybrid devices for quantum computing, the described methods are useful for fabricating any type of semiconductor device in which a pristine interface between a semiconductor component and a further component is desired.

[0119] It will be appreciated that the above embodiments have been described by way of example only.

[0120] More generally, according to one aspect disclosed herein, there is provided a method of fabricating a semiconductor device. The method includes providing a workpiece comprising a semiconductor structure, the semiconductor structure comprising a substrate and a semiconductor component arranged on a surface of the substrate; a capping layer over the semiconductor structure; and a shadow wall comprising a leg and a body connected to the leg. The capping layer is a layer of arsenic or antimony. The leg of the shadow wall extends from the semiconductor structure through an aperture in the capping layer. The body of the shadow wall is on the capping layer and over the semiconductor structure. The method further comprises removing the capping layer; and after removing the capping layer. depositing a further material onto a first region of the semiconductor structure. The shadow wall prevents deposition of the further material onto a second region of the semiconductor structure. The capping layer may protect the surface of the semiconductor component, and may be removed without degrading the quality of the surface of the semiconductor component. This may allow the further material to be deposited in an environment which is different from that in which the semiconductor structure is fabricated, while allowing a pristine interface between the semiconductor component and the further material to be obtained.

[0121] The first region may be referred to as an unshadowed region, and the second region may be referred to as a shadowed region.

[0122] The capping layer may be an in situ layer. An in situ layer is a layer formed in the same vacuum environment as the semiconductor component. When the capping layer is an in situ layer, the surface of the semiconductor component may be free of native oxides.

[0123] Providing the workpiece may include preparing the semiconductor structure, and depositing the capping layer over the semiconductor structure. Preparing the semiconductor structure may comprise growing the semiconductor component on a surface of the substrate. The preparation of the semiconductor structure and the deposition of the capping layer may be performed in a first environment. The first environment may comprise an ultra-high vacuum. The first environment may be in a chamber of a semiconductor growth apparatus.

[0124] The presence of shadow walls during growth of a semiconductor component may impose constraints on the growth, for example by restricting diffusion of atoms across the surface of the substrate. Growing the semiconductor component before forming the shadow wall may allow for a wider range of semiconductor components to be fabricated, and may allow for better optimization of growth conditions.

[0125] Providing the workpiece may further comprise forming the aperture by etching through the capping layer; applying a resist to fill the trench and cover the capping layer; and forming the shadow wall by selectively exposing the resist and developing the resist, with resist in the aperture being developed to form the leg, and resist over the capping layer being developed to form the body.

[0126] The resist may be an inorganic resist, for example hydrogen silsesquioxane. Carbon can act as a dopant for semiconductor materials, and avoiding the presence of carbon during deposition processes such as molecular beam epitaxy may therefore be advantageous.

[0127] Forming the aperture may comprise forming a mask over the capping layer by lithography, the mask having an opening which exposes a region of the capping layer; and etching the region of the capping layer exposed by the mask. In such implementations, the method further comprises, before removing the capping layer, removing the mask. The mask may be removed before applying the resist which fills the trench and covers the capping layer. Alternatively, the mask may be removed after forming the shadow wall and before removing the capping layer.

[0128] Alternatively, forming the aperture may comprise heating regions of the capping layer to sublimate the arsenic or antimony in the heated regions. For example, the aperture may be formed by laser ablation.

[0129] The semiconductor structure may be removed from the first environment before forming the aperture. For example, in implementations where the preparation of the semiconductor structure and the deposition of the capping layer are performed in a first apparatus, the method may further comprise, after depositing the capping layer and before removing the capping layer, removing the semiconductor structure from the first apparatus. Removing the semiconductor structure from the first apparatus may expose the semiconductor structure to air. The capping layer protects the semiconductor component from damage, allowing the semiconductor structure to be removed from a vacuum environment without degrading the semiconductor structure.

[0130] Forming the shadow wall may further comprise, after developing the resist, applying a second resist over the body; and selectively exposing and developing the second resist to extend the body. This may allow shadow walls with more complex three-dimensional shapes to be obtained. By varying the shape of the shadow wall, the locations at which the further material is deposited may be varied.

[0131] The semiconductor structure may include a trench, and the leg of the shadow wall may extend from the trench. Providing a trench in the semiconductor structure may allow for more robust attachment of the shadow wall to the semiconductor structure. The trench may, for example, have a depth of less than or equal to 30 nm.

[0132] The shadow wall may comprise a silicon oxide. Silicon oxides may have good compatibility with material deposition processes such as molecular beam epitaxy. To form a shadow wall comprising silicon oxide, a resist comprising hydrogen silsesquioxane may be used.

[0133] The further material may be deposited by a directional deposition process, such as molecular beam epitaxy. For example, the further material may be deposited from a direction perpendicular to the surface of the substrate. In other words, a zero-angle deposition process may be used. Depositing the further material from a direction perpendicular to the surface of the substrate may allow for high resolution deposition, i.e. a pattern of deposited material with clearly-defined edges may be obtained.

[0134] Removing the capping layer may comprise heating the capping layer under vacuum, optionally a high vacuum or ultra-high vacuum. Arsenic and antimony each sublime at moderate temperatures. Removal of the capping layer by heating may maintain a pristine surface on the semiconductor structure.

[0135] The shape of the shadow wall may be defined using lithographic techniques, for example by selectively exposing the resist to an electron beam. This may allow a high degree of control over the shape of the shadow wall. For example, the body of the shadow wall may include an aperture. Further material for forming an active region of a semiconductor device may then be deposited through the aperture. This may allow the active region to be spaced from the legs of the shadow wall. Spacing the active region from areas of the semiconductor structure which are exposed to etchant may improve the performance of the finished device. [0136] The method may further comprise forming a component on the shadow wall. The component may comprise a metal layer and a dielectric layer. The component may be a gate structure. The component may be a frame gate.

[0137] The capping layer may be an amorphous layer. Amorphous layers of arsenic or antimony may be deposited onto a wide range of different materials.

[0138] The method may further comprise, after depositing the further material, depositing a second capping layer over the semiconductor structure. The second capping layer may be a further layer of arsenic or antimony. It is contemplated that further shadow walls may then be formed over the semiconductor structure, to allow for control over the deposition of further materials.

[0139] The nature of the semiconductor component is not particularly limited and may be selected as appropriate depending on the nature of the device to be fabricated. For example, the semiconductor component may comprise a semiconductor heterostructure for hosting a 2-dimensional electron gas or a 2-dimensional hole gas. The semiconductor heterostructure may comprise a quantum well layer arranged between two barrier layers.

[0140] In other implementations, the semiconductor component may be obtainable by selective area growth. In such implementations, the semiconductor structure may further comprise a dielectric mask.

[0141] The semiconductor structure may comprise a lll-V semiconductor material. The lll-V semiconductor material may include arsenic and/or antimony as component(s). In such implementations, the arsenic or antimony source used in the growth of the semiconductor component may also be used in the formation of the capping layer.

[0142] Examples of suitable lll-V semiconductor materials include those of Formula 1: lnASxSbi- _x (Formula 1) where x is in the range 0 to 1. [0143] Further examples of lll-V semiconductor materials include materials of Formula 2: ln _y Ali-yAs _z Sbi- _z (Formula 2) where y is in the range 0 to 1, and z is in the range 0 to 1. The material of Formula 2 may be a quaternary material, in which both y and z are non-zero.

[0144] The nature of the further material is not particularly limited. The further material may comprise a metal, a dielectric material, a ferromagnetic insulator, or the like. For example, the further material may comprise a metal. Depositing a metal may form gate electrode(s), transmission lines, or the like on the semiconductor structure. The metal may be a superconductor. Since the methods provided herein are useful for maintaining the surface of the semiconductor component in a pristine state, the methods are well-suited for the fabrication of semiconductor-superconductor hybrid devices.

[0145] The method may be free of any etching steps following deposition of the further material.

[0146] In another aspect, the present invention provides the use of a layer of arsenic or antimony as a removable support for a body of a shadow wall, wherein the shadow wall further comprises a leg extending through an aperture in the layer. The layer may be arranged on or over a semiconductor structure, and may protect the semiconductor structure, in particular the surface of the semiconductor structure. Protecting the semiconductor structure may comprise preventing chemical changes to the semiconductor structure, such as preventing oxidation or hydrolysis. Protecting the semiconductor structure may comprise preventing contamination of the semiconductor structure, for example preventing sorption of species onto or into the semiconductor structure.

[0147] The use may be in the context of a method as described herein. The discussion of the various components and materials set out with respect to the method aspect are equally applicable to the use aspect. [0148] In another aspect, the present invention provides a workpiece, comprising a semiconductor structure, the semiconductor structure comprising a substrate and a semiconductor component arranged on a surface of the substrate; a capping layer over the semiconductor structure; and a shadow wall comprising a leg and a body connected to the leg. The capping layer is a layer of arsenic or antimony. The leg of the shadow wall extends from the semiconductor structure through an aperture in the capping layer. The body of the shadow wall is on the capping layer and over the semiconductor structure. The workpiece is an intermediate product, useful in the methods described herein. Providing a capping layer which is a layer of arsenic or antimony may allow the capping layer to be removed during subsequent processing without degrading the surface of the semiconductor component.

[0149] As will be appreciated, the discussion of the components and materials set out above with respect to the method aspect is equally applicable to the workpiece aspect.

[0150] For example, the semiconductor structure may include a trench, and the leg of the shadow wall may extend from the trench. As previously described, this may affix the shadow wall more robustly to the semiconductor structure.

[0151] The shadow wall may comprise a silicon oxide. Many deposition techniques, such as molecular beam epitaxy, may be performed in the presence of silicon oxide shadow walls. Silicon oxide does not degas when exposed to a vacuum environment.

[0152] Other variants or use cases of the disclosed techniques may become apparent to the person skilled in the art once given the disclosure herein. The scope of the disclosure is not limited by the described embodiments but only by the accompanying claims.