BACKGROUND

[0001] In many applications, transistors should have a relatively low specific resistance. For some field-effect-transistors, such as drain-extended metal-oxide-semiconductor (DEMOS) transistors, increasing the oxide thickness over part of the gate oxide may lower specific resistance. SUMMARY

[0002] In at least one example, a method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the anti -reflective coating below the opening in the photoresist layer; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent after etching the portion of the barrier layer below the opening to grow an oxide region; removing the barrier layer after providing the ambient oxidizing agent; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

[0003] In at least one example, a method to fabricate a transistor comprises: forming a sacrificial oxide layer on a semiconductor substrate; depositing a silicon nitride layer on the sacrificial oxide layer; depositing an anti -reflective coating on the silicon nitride layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the anti-reflective coating below the opening; etching a portion of the silicon nitride layer below the opening to expose a portion of the sacrificial oxide layer; and growing an oxide region on the exposed portion of the sacrificial oxide layer; removing the silicon nitride layer after growing the oxide region; implanting dopants into the semiconductor substrate after removing the silicon nitride layer; removing the sacrificial oxide layer after implanting dopants into the semiconductor substrate; and forming a gate oxide layer on the semiconductor substrate after removing the sacrificial oxide layer, wherein the oxide region is grown to thickness greater than a thickness of the gate oxide layer.

[0004] In at least one example, a method to fabricate a transistor comprises: forming a sacrificial oxide layer on a semiconductor substrate; depositing a silicon nitride layer on the sacrificial oxide layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the silicon nitride layer below the opening to expose a portion of the sacrificial oxide layer; growing an oxide region of at least 400 angstroms thick on the exposed portion of the sacrificial oxide layer; removing the silicon nitride layer after growing the oxide region; implanting dopants into the semiconductor substrate after removing the silicon nitride layer to form a drain region in the semiconductor substrate; removing the sacrificial oxide layer after implanting dopants into the semiconductor substrate; and forming a gate oxide layer on the semiconductor substrate after removing the sacrificial oxide layer, the gate oxide layer having a thickness less than 400 angstroms.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 shows a transistor in various examples.

[0006] FIG. 2 shows a semiconductor substrate with several layers in various examples.

[0007] FIG. 3 shows a silicon substrate after etching in various examples.

[0008] FIG. 4 shows a silicon substrate with an oxide region in various examples.

[0009] FIG. 5 shows a process flow in various examples.

[0010] FIG. 6 shows two transistors in various examples.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0011] In the described embodiments, a method to fabricate transistors, such as a DEMOS transistor, includes growing a thick oxide below the transistor gate, where the process steps can be incorporated into a standard bipolar complementary-metal-oxide-semiconductor (BiCMOS) process flow.

[0012] FIG. 1 shows a cross-sectional view of an example transistor 100, not drawn to scale. In the example of FIG. 1, the example transistor 100 is a DEMOS transistor. A drain region 104 and a source region 106 are formed in a semiconductor substrate 102. In the example of FIG. 1, the semiconductor substrate 102 is a silicon crystal, and the example transistor 100 is an n-type DEMOS transistor, where the drain region 104 and the source region 106 are each highly doped n- type regions. The source region 106 is formed within a lightly doped p-type well 108, and the drain region 104 is extended by way of the lightly doped n-type region 110.

[0013] A dielectric layer 112 is formed on the semiconductor substrate 102. The dielectric layer 112 is usually silicon dioxide, and the dielectric layer 112 is referred to as a gate oxide layer 112. A gate 114 is formed over the gate oxide layer 112. The gate 114 may comprise polysilicon. An oxide region 116 is grown on and into the semiconductor substrate 102. The oxide region 116 is adjacent to the drain region 104 and is below the gate 114, and the oxide region 116 is thicker than the dielectric layer 112. The oxide region 116 may comprise silicon dioxide. The presence of the oxide region 116 provides a lift-up to the gate 114. A highly doped p-type region 118 serves as a body contact for the example transistor 100.

[0014] When the example transistor 100 is ON, so that the channel below the gate 114 is in an inversion mode, a channel current of majority carriers (e.g., electrons for an n-type channel) flows from the source region 106 to the drain region 104. The presence of the oxide region 116 affects the path of the channel current. The relatively large depth of the oxide region 116 into the channel forces the majority carriers of the channel current to accelerate as they move underneath the oxide region 116 and toward the drain region 104. The acceleration of the majority carriers helps to reduce the specific resistance of the example transistor 100.

[0015] The oxide region 116 may be employed in other types of transistors, such as a double-diffusion metal-oxide-semiconductor (DMOS) transistor, as well as other types of lateral or vertical transistors. Although not shown in FIG. 1, other semiconductor devices may be formed in the semiconductor substrate 102 and coupled to the example transistor 100 to realize various circuits. In some embodiments in which other semiconductor devices are integrated with the example transistor 100, a silicon trench isolation (STI) region is formed around the example transistor 100 to provide electrical isolation from other semiconductor devices.

[0016] FIG. 2 shows a cross-sectional view (not drawn to scale) of the semiconductor substrate 102 and several layers formed during part of a process flow according to embodiments. A sacrificial dielectric layer 204 is formed over the semiconductor substrate 102. In silicon technology, the sacrificial dielectric layer 204 typically comprises silicon dioxide, and will be referred to as a sacrificial oxide layer 204. A barrier layer 206, typically silicon nitride, is deposited on the sacrificial oxide layer 204. A bottom antireflective coating (BARC) 208 is deposited on the barrier layer 206, and a photoresist layer 210 is deposited on the BARC 208.

[0017] The photoresist layer 210 is exposed to radiation according to an illumination pattern defined by a mask (not shown). The pattern illuminated on the photoresist layer 210 defines an opening for growing the oxide region 116 of FIG. 1. In the example of FIG. 2, arrows, such as an arrow 212, pictorially represent the radiation. In some embodiments, the radiation may be in the deep ultraviolet (DUV) region, such as, for example, a wavelength of 248 nm, or a wavelength of 193 nm for an argon fluoride excimer laser source. As process technology nodes move to smaller sizes, embodiments may utilize other types of illumination sources and masks, such as extreme ultraviolet (EUC) lasers used with reflective masks (not shown).

[0018] FIG. 2 does not show all features formed within and on the semiconductor substrate 102. For example, buried layers and STI regions may be formed to electrically isolate various devices formed within and on the semiconductor substrate 102.

[0019] FIG. 3 shows a cross-sectional view (not drawn to scale) of the silicon substrate 102, with the layers of FIG. 2, after etching is performed to provide an opening 302, according to embodiments. The etching may include plasma reactive-ion etching (RIE). The plasma RIE may be performed in a gas mixture of oxygen (0 ₂ ), a carrier gas (e.g., argon), or fluorocarbons comprising carbon (C), Hydrogen (H), and Fluorine (F) having a stoichiometry CxHyFz with x = 1 or 2; y = 0, 1, 2, 3, or 4; and z = 1, 2, 3, or 4.

[0020] FIG. 4 shows a cross-sectional view (not drawn to scale) of the silicon substrate 102, with the layers of FIG. 3, where the oxide region 116 has been grown, according to embodiments. For some embodiments, the oxide region 116 may have a thickness of at least 400 angstroms, for example in the range of 400 angstroms to 4000 angstroms. The semiconductor substrate 102 is exposed to an ambient oxidizing agent to grow the oxide region 116. For some embodiments, the ambient oxidizing is performed in a thermal furnace oxidation process using oxygen and/or steam. For some embodiments, the semiconductor substrate 102 is exposed to oxygen and/or steam at a temperature above 900°C, for example in the range of 950°C to l000°C.

[0021] The thickness of the barrier layer 206 affects formation of the“bird’s beak” (also sometimes referred to as a“birds beak”) shape of the oxide region 116 because of lateral oxidation under the barrier layer 206. The thickness of the barrier layer 206 may have a thickness from 300 angstroms to 1000 angstroms. In some embodiments, the barrier layer 206 may be about 950 angstroms thick.

[0022] After forming the oxide region 116, the various layers (excluding the oxide region 116) above the semiconductor substrate 102 illustrated in FIG. 4 are removed, followed by additional process steps to fabricate a transistor, such the example transistor 100 of FIG. 1. For example, dopants can be implanted to form the lightly doped n-type region 110, the drain region 104, and the source region 106. The sacrificial oxide layer 204 is removed before growing the gate oxide layer 112, and the gate 114 is formed over the gate oxide layer 112.

[0023] FIG. 5 shows an example process flow 500. The example process flow 500 includes, in step 501, formation of one or more STI regions; in step 502, forming a first dielectric layer (e.g., the sacrificial oxide layer 204) on a semiconductor substrate (e.g., the semiconductor substrate 102); in step 504, depositing a barrier layer 206 (e.g., a silicon nitride layer) on the first dielectric layer; in step 506, depositing an anti-reflective coating (e.g., the BARC 208) on the barrier layer; in step 508, depositing a photoresist layer (e.g., the photoresist layer 210); in step 510, exposing a pattern in the photoresist layer to radiation; in step 512, etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; in step 514, etching a portion of the anti- reflective coating below the opening in the photoresist layer; in step 516, etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; in step 518, providing an ambient oxidizing agent after etching the portion of the barrier layer below the opening; in step 520, removing the barrier layer after providing the ambient oxidizing agent; in step 522, implanting dopants into the semiconductor substrate after removing the barrier layer (e.g., to form the drain region 104 or the source region 106); in step 524, removing the first dielectric layer after implanting dopants into the semiconductor substrate; and in step 526, forming a second dielectric layer (e.g., the gate oxide layer 112) after removing the first dielectric layer.

[0024] The process steps in fabricating a transistor according to embodiments (e.g., the process flow 500) can be incorporated into a standard process flow, for example, a standard BiCMOS process, or a linear BiCMOS (LBC) process. Additional process steps may be performed before and after the process steps in an embodiment, such as the process steps described with respect to FIG. 5. For example, implanting dopants into the semiconductor substrate 102 to form buried regions may be performed before the process flow 500. As another example, an epitaxial layer may be grown on the semiconductor substrate 102 before the process flow 500.

[0025] Some or all of the steps illustrated in FIG. 5 may be repeated when fabricating multiple devices on a wafer. For example, step 526 (and steps related to step 526) may be repeated to fabricate multiple transistors having different thicknesses for their respective gate oxide layers. As a specific example, the dielectric layer formed in an iteration of step 526 may have a thickness of about 40 angstroms, so that one or more transistors are fabricated having a gate oxide layer of about 40 angstroms. In another iteration of step 526, the dielectric layer may have a thickness of about 100 angstroms, so that one or more transistors are fabricated having a gate oxide layer of about 100 angstroms, suitable for a higher operating voltage.

[0026] FIG. 6 shows a cross-sectional view (not drawn to scale) of two example transistors. FIG. 6 shows a semiconductor substrate 602 in which the example transistor 100 is formed, but where the highly doped p-type region 118 (body contact) is not shown. Formed in the semiconductor substrate 602 is an example transistor 600 (with its body contact not shown). An STI region 601 isolates the example transistor 100 from the example transistor 600.

[0027] The example transistor 600 comprises a drain region 604 and a source region 606. In the example of FIG. 6, the example transistor 600 is an n-type DEMOS transistor, where the drain region 604 and the source region 606 are each highly doped n-type regions. The source region 606 is formed within a lightly doped p-type well 608, and the drain region 604 is extended by way of the lightly doped n-type region 610.

[0028] A gate oxide layer (a dielectric layer) 612 is formed on the semiconductor substrate 602. A gate 614 is formed over the gate oxide layer 612. An oxide region 616 is grown on and into the semiconductor substrate 602. The oxide region 616 is adjacent to the drain region 604 and is below the gate 614, and the oxide region 616 is thicker than the gate oxide layer 612. The gate oxide layer 612 is thicker than the gate oxide layer 112, so that the example transistor 600 can withstand a higher operating voltage than the example transistor 100.

[0029] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.