METHOD FOR FILTERING USED IN A DIGITAL PHASE LOCKED LOOP

Title:

METHOD FOR FILTERING USED IN A DIGITAL PHASE LOCKED LOOP

Document Type and Number:

WIPO Patent Application WO/2001/059931

Kind Code:

A1

Abstract:

The invention discovered a filter method used in a digital phase locked loop. The method includes: determining a desired value of phase difference between an input clock and local regenerator clock; calculating the phase difference between them by a subtracter; comparing the phase difference with the desired value of phase difference; adjusting the local regenerator clock for stabilizing the phase difference at a desired value. When the local regenerator clock is adjusted, phase difference is divided into difference section according to the desired value of phase difference so as to the phase change rate of local regenerator clock is the least in the range of desired value of phase difference; the more far away section from the desired value of phase difference, the more faster the phase change rate of local regenerator clock is. Because simultaneously consider error code and the least jitter, the sufferance of the jitter is enhanced and the jitter transform characteristic is superiority, and the performance in true put jitter has been improved in the range of low frequency and high frequency.

Inventors:

HE TINGBO (CN)

Application Number:

PCT/CN2001/000068

Publication Date:

August 16, 2001

Filing Date:

January 20, 2001

Export Citation:

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Assignee:

HUAWEI TECH CO LTD (CN)
HE TINGBO (CN)

International Classes:

H03L7/085; H03L7/099; H04J3/07; (IPC1-7): H03L7/085

Domestic Patent References:

WO1997015118A1

1997-04-24

Foreign References:

US5619543A	1997-04-08
US5036294A	1991-07-30
US5745001A	1998-04-28
US5033064A	1991-07-16

Other References: