[0001] The present invention relates a method for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network, wherein the packet processing system comprises a programmable packet switching processor and a traffic shaping processor. [0002] Furthermore, the present invention relates to a telecommunications network for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network, wherein the packet processing system comprises a programmable packet switching processor and a traffic shaping processor. [0003] Additionally, the present invention relates to a system for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network, wherein the packet processing system comprises a programmable packet switching processor and a traffic shaping processor.

[0004] Furthermore, the present invention relates to a program, and a computer program product for an improved traffic shaping and/or management of IP traffic in a packet processing system.

[0005] The exchange of packetized information in broadband communication systems or telecommunications networks, both in fixed-line as in wireless communication systems (or fixed-line communication networks and mobile communication networks) has already grown dramatically and probably will also grow in the future, especially due to the rapid spread of various data services as well as applications in such communication networks.

[0006] Currently, commercial off-the-shelf network packet processing chips or integrated circuits, which are typically used in high-performance network switches, are used to process and forward payload to serve subscribers connected to a telecommunications network. [0007] Such network packet processing chips or integrated circuits, also called ASICs (application-specific integrated circuit), commonly support a fixed functionality and a limited scalability of packet queueing (e.g. regarding depth or number of queues) only. However, queueing requirements in a network might exceed, and typically does exceed the capabilities of such conventionally known network packet processing chips or integrated circuits.

[0008] Moreover, queueing is required in networking devices in order to buffer packets until they can be sent. Typically, this is very important before network links with limited bandwidth in order to guarantee a link utilization of almost 100%.

SUMMARY

[0009] An object of the present invention is to provide a technically simple, effective and cost effective solution for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network. A further object of the present invention is to provide a corresponding telecommunications network, a corresponding system, and a corresponding program and computer program product.

[0010] The object of the present invention is achieved by a method for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network, wherein the packet processing system comprises a programmable packet switching processor and a traffic shaping processor, wherein data packets - received by the packet processing system - are ingressed to the packet switching processor, and wherein data packets - transmitted by the packet processing system - are egressed by the traffic shaping processor, wherein for an improved traffic shaping and/or management of IP traffic, the method comprises the following steps:

-- in a first step, a number of considered data packets, after or while being received by the packet processing system, are received by or ingressed to the packet switching processor,

-- in a second step, subsequent to the first step, the packet switching processor processes the number of considered data packets, appends a queue identification information to each one of the considered data packets, and transmits the considered data packets to the traffic shaping processor,

-- in a third step, subsequent to the second step, the traffic shaping processor applies traffic shaping to the considered data packets by means of using the respective queue identification information of each one of the considered data packets to select a queue for each one of the considered data packets, respectively, and

-- especially such that a multitude of data consumers can be provided with data packets (50) in parallel and/or

-- especially by means of using a number of queues exceeding 10.000 queues, wherein each one of said queues has a depth or a storing capacity of more than 10 MB, and applying an advanced scheduling algorithm which is not supported by common packet processing systems, especially a hierarchical scheduling a hierarchical scheduling of the considered data packets.

[0011] It is thereby advantageously possible according to the present invention to overcome the aforementioned restriction (of unsatisfactory queueing capabilities) of the prior art by introducing - in a packet processing system, and besides a packet switching processor - an additional, second-stage processing apparatus, or traffic shaping processor (for example in the form of an ASIC or a programmed FPGA, field programmable gate array) which processes and queues packets after they have been processed by the packet switching processor (or first-stage ASIC) with insufficient queueing capabilities. This forms a system, or packet processing system, of two processing components (packet processing system and traffic shaping processor) where the first one does header processing and packet classification, and the second one is dedicated to queueing functions in sufficient scales.

[0012] It is especially preferred that the traffic shaping processor comprises resources to handle a very large number of queues, at least 10.000 queues, but typically providing the capabilities for more than 10.000 queues, preferably more than 50.000 queues, still preferably more than 100.000 different queues, still more preferably more than 200.000 queues, still more preferably more than 400.000 queues, and still more preferably more than 800.000 queues; in all these cases the number of available queues is as large as possible, especially one million queues, or 10 million queues, or 100 million queues. Additionally, not only the number of queues is comparatively large according to the present invention, but also their depth - i.e. the capabilities, especially for each one of the large number of queues, to store many data packets and/or many data packets which have a comparatively large size. According to the present invention, especially a storing capacity of each of the queues of the inventive packet processing system corresponds to 10 MB or more than 10 MB, preferably corresponds to 20 MB or more than 20 MB, still preferably corresponds to 50 MB or more than 50 MB, still preferably corresponds to 100 MB or more than 100 MB; in all these cases the storing capacity of each of the queues of the inventive packet processing system is as large as possible, especially 200 MB, or 1GB, or 10 GB. The total required memory of the whole shaping processor is a junction of the individual queues and thereby multiple GBs (maybe up to 100GB in future, currently up to 1 GB) can be reached.

[0013] According to the present invention, the proposed system (or packet processing system, comprising at least one packet switching processor and at least one traffic shaping processor) provides the performance and scalability of current programmable ASICs, but - unlike the state of the art - it also provides the necessary flexibility to offer large-scale traffic shaping, e.g. required in access networks, comprising the required number of queues, as well as the required queue depth, as well as hierarchical scheduling capabilities of the considered data packets.

[0014] Data packets according to the present invention are especially, but not necessarily, IP traffic packets, or Ethernet packets, or GEM (GPON encapsulation method) frames - all of which typically also comprise IP traffic packets. Conventionally known hardware switches commonly process packets using a special ASIC which is only designed for packet processing and forwarding.

[0015] According to conventionally known systems, since the introduction of the programming language P4 in 2014, a trend towards ASICs with reconfigurable data planes has arisen - e.g. Barefoot Networks currently offers a P4 programmable chip which has a fully programmable pipeline. However, these presently known languages only describe the behavior of the match-action pipeline and do not cover the queueing behavior of these chips. Until now, the queueing behavior is commonly reconfigured within hardware limitations of the chip over a vendor-specific interface. Typically this does not provide the queueing capabilities required especially in access networks, i.e. comprising, in combination, the required number of queues, as well as the required queue depth, as well as hierarchical scheduling capabilities.

Regarding the number of queues and the queue depth in conventionally known systems: Queued packets must be stored in memory on the switch hardware. Typically, this can be done either in internal memory of the ASIC which is implemented with SRAM, or outside the chip in DRAM. SRAM typically provides a rather low capacity in the range < 50 to 70 MB even in devices with highest performance due to technological limitations. When packets are stored outside the chip in DRAM, the size thereof is usually much higher in a scale of n*16GB. However, this memory technology requires pins to interconnect the ASIC and the memory, and furthermore, the bandwidth is commonly much lower than on SRAM, and the latency is usually higher (by technological reasons). The additional pins required by the switching ASIC is the primary reason why most chips have only internal SRAM memory. In conventionally known systems, this is sufficient for most use cases and no external memory is needed. Another solution of conventionally known systems consists of using high bandwidth memory (HBM) (instead of external memory outside the package of the chip): This HBM is placed inside the package next to the ASIC, and, hence, no additional package pins are required.

The queueing capabilities themselves are a further restriction of most packet switching ASICs in conventionally known systems: In most use-cases according to the state of the art, the applications require only a few queueing capabilities, and, hence, the available queueing capability are sufficient.

[0016] However, according to the present invention and with the inventive packet processing system (comprising a packet switching processor and a separate traffic shaping processor), new applications requiring more features, like queueing at the service edge of ISPs, become possible. This especially regards the following features, especially the combination thereof:

-- support for “many queues”: typically conventionally known switches have less than 10.000 queues, often only around 10 queues per egress port; however, carriers (or network operators) - in order to provide queueing at the service edge of their networks - typically require hundreds of thousands of queues which typically and especially should be provided not to be bound to a dedicated port.

-- sophisticated scheduling mechanisms, especially in combination with a large number of queues: scheduling decides which queue should be served next (different scheduling mechanism are typically applied, e.g. Round-Robin (RR), Weighted Round-Robin (WRR), etc.); it is especially relevant to provide the capability for simple rate limiting (each queue can have a maximum rate (either bytes per second or packets per second), and the scheduler (or scheduling mechanism) guarantees that this limit is not exceeded), and/or for hierarchical rate limiting, especially of up to 6 hierarchical layers (thereby, especially in addition to simple rate limiting, additional rate limits are applied with respect to groups of queues; e.g. five queues (each rate limited at, e.g., 1 Mbit/s) should not exceed a total bandwidth of 2 Mbit/s.

-- Active Queue Management (AQM): In order to create high throughputs with affordable latencies, algorithms, called (active) queue management algorithms, are able to be used according to the present invention (conventionally known switches only support basic algorithms like taildrop, Random Early Detection (RED) or Weighted Random Early Detection (WRED); newer algorithms, e.g. Controlled Delay (CoDel, RFC 8289) and Proportional Integral Controller Enhanced (PIE, RFC 8033), cannot be added by a configuration update and require new hardware).

-- accounting capability: The egress traffic of the queues needs to be accounted (i.e. the number of bytes and packets (typically cumulatively) counted) which is not possible using conventionally known systems in combination with large numbers of queues (as such conventionally known systems, while providing the possibility of counters, do, at maximum, provide for a limited queue number, and, hence, a limited number of counters in the ASIC). [0017] According to the present invention, a solution is proposed that addresses the above mentioned challenges, i.e. support for large numbers of queues combined with sophisticated scheduling mechanisms, active queue management, and also the possibility to provide for accounting capabilities. According to the present invention, an improved traffic shaping and/or management of IP traffic is possible in a packet processing system, especially as part of a telecommunications network, by means of the packet processing system comprising the programmable packet switching processor and the traffic shaping processor. Thereby, data packets - received by the packet processing system - are ingressed to the packet switching processor, and egressed by the traffic shaping processor. For an improved traffic shaping and/or management of IP traffic, the method comprises the steps of:

-- in a first step, receiving data packets by the packet switching processor, i.e. a number of considered data packets are, after or while being received by the packet processing system, received by or ingressed to the packet switching processor,

-- in a second step, subsequent to the first step, processing and transmitting the data packets to the traffic shaping processor and thereby appending a queue identification information, i.e. the packet switching processor processes the number of considered data packets, appends a queue identification information to each one of the considered data packets, and transmits the considered data packets to the traffic shaping processor,

-- in a third step, subsequent to the second step, applying traffic shaping (and especially also doing accounting tasks), i.e. the traffic shaping processor applies traffic shaping to the considered data packets by means of using the respective queue identification information of each one of the considered data packets to select a queue for each one of the considered data packets, respectively, and by means of:

-- using a number of queues exceeding 10.000 queues, wherein each one of said queues has a depth or a storing capacity of more than 10 MB,

-- applying a hierarchical scheduling of the considered data packets. [0018] The telecommunications network according to the present invention might be a fixed-line telecommunications network or a mobile communication network but preferably is a telecommunications network having both aspects (or parts) of a fixed-line telecommunications network (or being a fixed-line telecommunications network in such parts) and aspects (or parts) of a mobile communication network (or being a mobile communication network in such parts); such networks are also known under the term fixed-mobile-convergence networks (FMC networks).

[0019] According to the present invention, it is advantageously possible and preferred that the data consumers are subscribers of an aggregation network, wherein the aggregation network comprises a network node or network element, especially a broadband network gateway element, wherein the packet processing system comprising the programmable packet switching processor and the traffic shaping processor is preferably part of the network node or network element.

[0020] It is thereby advantageously possible to apply the inventive concept in an aggregation network and/or a network node or network element of an aggregation network, serving, especially, a large number of customers or subscribers.

[0021] According to the present invention, it is advantageously furthermore possible and preferred that - in the third step - the traffic shaping processor applies traffic shaping to the considered data packets by means of using the respective queue identification information, and by means of:

-- using a number of queues exceeding 10.000 queues, wherein each one of said queues has a depth or a storing capacity of more than 10 MB,

-- applying a hierarchical scheduling of the considered data packets.

[0022] According to the present invention, it is advantageously possible and preferred that the hierarchical scheduling comprises or encompasses:

-- performing or executing a scheduling decision, based on rate limits with hierarchical dependencies, while considering different Quality of Service (QoS) classes, or -- performing or executing a scheduling decision, based on rate limits with hierarchical dependencies, while considering different Quality of Service (QoS) classes, and while treating QoS-classes differently dependent on the interfering hierarchical scheduler layer.

[0023] By means of applying hierarchical scheduling according to these features, it is advantageously possible to comparably easily take the scheduling decision (i.e. which packet should be sent next) taking into consideration the relevant factors, i.e. rate limits with hierarchical dependencies considering different Quality of Service (QoS) classes, or rate limits with hierarchical dependencies considering different Quality of Service (QoS) classes, and additionally treating QoS-classes differently dependent on the interfering hierarchical scheduler layer.

[0024] According to the present invention, it is advantageously possible and preferred that each specific one of the considered data packets is - besides being related to its assigned or selected queue:

-- related to a specific traffic class out of a plurality of different traffic classes, and -- related to a specific user or customer of the telecommunications network of a plurality of users or customers of the telecommunications network, and -- related to a first specific network node of the telecommunications network, and to at least a second specific network node of the telecommunications network, the first specific network node relating to a first stage of the access aggregation network, and the at least second specific network node relating to a second stage of the access aggregation network, and wherein applying the hierarchical scheduling of the considered data packets involves a scheduling that simultaneously takes into account the relation of each one of the considered data packets to the assigned or selected queue, and its specific traffic class, and its specific user or customer, and its first and second specific network node.

[0025] By means of applying such an hierarchical scheduling of the considered data packets (i.e. simultaneously taking into account the relation of each one of the considered data packets to the respective queue, the respective traffic class, the respective user or customer, and the respective first and second specific network node) it is advantageously possible to implement a manner of scheduling and traffic shaping that is appropriate and adapted to implement at the service edge of internet service provider’s networks. [0026] Furthermore, it is advantageously possible and preferred according to the present invention that the hierarchical scheduling of the considered data packets involves applying a rate limit regarding the considered data packets with respect to the assigned or selected queue, the specific traffic class, the specific user or customer as well as both the first and second specific network nodes, respectively. [0027] By means of applying a rate limit regarding the considered data packets (especially with respect to the assigned or selected queue, the specific traffic class, the specific user or customer as well as both the first and second specific network nodes) it is advantageously possible to define - by means of performing the traffic shaping and scheduling - the IP traffic with respect to individual network elements on different network layers or levels, and thereby especially assure that maximum throughput limits (of such network elements) are respected, i.e. not exceeded.

[0028] Furthermore, and according to an alternative embodiment of the present invention, it is preferred that the traffic shaping processor additionally applies traffic shaping to the considered data packets by means of using active queue management, especially using one or a plurality of the following algorithms: taildrop, Random Early Detection (RED) or Weighted Random Early Detection (WRED), Controlled Delay, CoDel, and Proportional Integral Controller Enhanced, PIE and/or especially by means of at least one out of the following: -- actively dropping data packets,

-- raising explicit congestion notification, ECN, flags, and

-- attaching more advanced congestion information to the data packets..

[0029] By means of using active queue management, it is advantageously possible to further render the traffic shaping and/or management of IP traffic in the packet processing system more stable, more secure and more flexible.

[0030] According to a further preferred embodiment of the present invention, the traffic shaping processor additionally provides a counting of the egress traffic of the queues, especially by means of counting the number of bytes and/or the number of packets, wherein said counting is performed independently for each of the queues of the traffic shaping processor.

[0031] By means of providing a counting of the egress traffic of the different queues, it is advantageously possible according to the present invention to easily provide for accounting capabilities within the packet processing system.

[0032] According to further embodiments of the present invention, the queue identification information, appended to each one of the considered data packets, is part of the considered data packets, respectively, especially positioned in front of the Ethernet header or between the Ethernet and the IP header, and wherein the traffic shaping processor removes the queue identification information from the considered data packets prior to storing the considered IP traffic packet in the selected or specified queue, respectively.

[0033] By means appending the queue identification information to each one of the considered data packets and being part of the considered data packets, it is advantageously possible that the packet switching processor part of the packet processing system is able to communicate with the traffic shaping processor part of the packet processing system.

It is advantageous to place the queue identification information in the front (in the first bits or bytes) of the (or each) packet or data packet; this makes it easier for the shaping processor to extract and remove this information - hence no complex packet parsing is needed. Additionally, a complicated lookup (e.g. based on IP addresses of the packet) would need to be performed inside the shaping processor; such a lookup requires correspondingly capable hardware.

[0034] Furthermore, it is advantageously possible and preferred according to the present invention that the queue identification information corresponds to a simple consecutive number, or different parts of the queue identification information have different meanings, especially different shared links/resources in an access tree.

[0035] Thereby, it is advantageously possible to provide for an efficient communication between the packet switching processor part of the packet processing system and the traffic shaping processor part of the packet processing system.

[0036] Furthermore, and according to an alternative embodiment of the present invention, it is preferred that the first specific network node of the telecommunications network corresponds to an access node, especially a DSLAM node, Digital Subscriber Line Access Multiplexer node, serving the specific user or customer, and/or wherein the second specific network node of the telecommunications network corresponds to broadband network gateway serving the specific user or customer.

[0037] Furthermore, the present invention relates to a telecommunications network for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of the telecommunications network, or system for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network, wherein the packet processing system comprises a programmable packet switching processor and a traffic shaping processor, wherein data packets - received by the packet processing system - are ingressed to the packet switching processor, and wherein data packets - transmitted by the packet processing system - are egressed by the traffic shaping processor, wherein for an improved traffic shaping and/or management of IP traffic, the telecommunications network or the system is configured such that:

-- a number of considered data packets, after or while being received by the packet processing system, are received by or ingressed to the packet switching processor,

-- the packet switching processor processes the number of considered data packets, appends a queue identification information to each one of the considered data packets, and transmits the considered data packets to the traffic shaping processor, -- the traffic shaping processor applies traffic shaping to the considered data packets by means of using the respective queue identification information of each one of the considered data packets to select a queue for each one of the considered data packets, respectively, and

-- especially by means of: using a number of queues exceeding 10.000 queues, wherein each one of said queues has a depth or a storing capacity of more than 10 MB, and applying a hierarchical scheduling of the considered data packets, and/or -- especially such that a multitude of data consumers can be provided with data packets in parallel.

[0038] Furthermore, the present invention relates to a network node or network element, especially broadband network gateway element, for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network, the network node or the network element comprising the packet processing system, wherein the packet processing system comprises a programmable packet switching processor and a traffic shaping processor, wherein data packets - received by the packet processing system - are ingressed to the packet switching processor, and wherein data packets - transmitted by the packet processing system - are egressed by the traffic shaping processor, wherein for an improved traffic shaping and/or management of IP traffic, the network node or network element is configured such that:

-- a number of considered data packets, after or while being received by the packet processing system, are received by or ingressed to the packet switching processor,

-- the packet switching processor processes the number of considered data packets, appends a queue identification information to each one of the considered data packets, and transmits the considered data packets to the traffic shaping processor,

-- the traffic shaping processor applies traffic shaping to the considered data packets by means of using the respective queue identification information of each one of the considered data packets to select a queue for each one of the considered data packets, respectively, and -- especially by means of: using a number of queues exceeding 10.000 queues, wherein each one of said queues has a depth or a storing capacity of more than 10 MB, and applying a hierarchical scheduling of the considered data packets, and/or -- especially such that a multitude of data consumers can be provided with data packets in parallel.

[0039] Additionally, the present invention relates to a system for an improved traffic shaping and/or management of IP traffic in a packet processing system, especially as part of a telecommunications network, wherein the packet processing system comprises a programmable packet switching processor and a traffic shaping processor, wherein data packets - received by the packet processing system - are ingressed to the packet switching processor, and wherein data packets - transmitted by the packet processing system - are egressed by the traffic shaping processor, wherein for an improved traffic shaping and/or management of IP traffic, the telecommunications network is configured such that:

-- a number of considered data packets, after or while being received by the packet processing system, are received by or ingressed to the packet switching processor,

-- the packet switching processor processes the number of considered data packets, appends a queue identification information to each one of the considered data packets, and transmits the considered data packets to the traffic shaping processor,

-- the traffic shaping processor applies traffic shaping to the considered data packets by means of using the respective queue identification information of each one of the considered data packets to select a queue for each one of the considered data packets, respectively, and by means of:

-- using a number of queues exceeding 10.000 queues, wherein each one of said queues has a depth or a storing capacity of more than 10 MB, -- applying a hierarchical scheduling of the considered data packets.

[0040] Still additionally, the present invention relates to a program comprising a computer readable program code which, when executed on a computer and/or on a network node of a telecommunications network and/or on a packet processing system, or in part on a network node of a telecommunications network and in part on a packet processing system, causes the computer and/or the network node of a telecommunications network and/or the packet processing system to perform the inventive method.

[0041] Furthermore, the present invention relates to a computer program product for an improved traffic shaping and/or management of IP traffic in a packet processing system, the computer program product comprising a computer program stored on a storage medium, the computer program comprising program code which, when executed on a computer and/or on a network node of a telecommunications network and/or on a packet processing system, or in part on a network node of a telecommunications network and in part on a packet processing system, causes the computer and/or the network node of a telecommunications network and/or the packet processing system to perform the inventive method.

[0042] These and other characteristics, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. The description is given for the sake of example only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS [0043] Figure 1 schematically illustrates a packet processing system according to the present invention, comprising a packet switching processor or packet switching processor part as well as a traffic shaping processor or traffic shaping processor part.

[0044] Figure 2 schematically illustrates an example of a queue identification information to be appended, according to the present invention, to a IP traffic packet by the packet switching processor, and, later on, used by the traffic shaping processor to provide for a corresponding traffic shaping and scheduling.

[0045] Figure 3 schematically illustrates a representation of further details of a traffic shaping processor according to the present invention.

DETAILED DESCRIPTION

[0046] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. [0047] Where an indefinite or definite article is used when referring to a singular noun, e.g. “a”, “an”, “the”, this includes a plural of that noun unless something else is specifically stated.

[0048] Furthermore, the terms first, second, third and the like in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. [0049] In Figure 1, a packet processing system 10 according to the present invention is schematically illustrated. The packet processing system 10 comprises a packet switching processor 20 or packet switching processor part 20 as well as a traffic shaping processor 40 or traffic shaping processor part 40. The packet switching processor 20 is especially provided as a P4 processor or P4 capable processor. The traffic shaping processor 40 especially comprises a multiplexer, a multitude of different queues (typically more than 100.000), and different pieces of runtime configuration information (such as, e.g., a transmission rate to be applied, a burst size per queue, etc.), as well as an arbiter or algorithm.

[0050] The architecture of the packet processing system 10 (with its at least two part of the packet switching processor 20 and the traffic shaping processor 40) provides for a queueing disaggregation (from packet switching) by means of two different parts or portions, especially two different chips or integrated circuits.

[0051] The placement or assembly of these two (or more) chips (or integrated circuits, i.e. the two different parts or portions) can be either in the same ASIC package, in the same device (e.g. one switch case) or in different devices. All these designs have different advantages and disadvantages:

According to a first alternative embodiment, the two different parts or portions are located or arranged in the same package: This means, both chips are manufactured within the same package (i.e. an arrangement that is comparatively similar to the typical location or arrangement of High-Bandwidth Memory (HBM)). The advantage of such an embodiment is that no additional package pins are needed; the disadvantage is that such an arrangement is typically expensive for small production numbers.

According to a second alternative embodiment, the two different parts or portions are located or arranged in or as part of the same device or same board: This means that both chips integrated circuits (that are separated but) placed on the same printed circuit board (PCB), also known as “mainboard”. This means that the chips, including the package, are off-the-shelf hardware; the pins of the chip are electrically directly attached; no expensive wires (like in the third alternative embodiment) are needed to connect the chips. However, a special device needs to be built, but on-demand manufacturers are able to do that even for comparatively low production numbers.

According to a third alternative embodiment, the two different parts or portions hosted by two different devices, i.e. they are placed closely together and are connected by cables (e.g. Ethernet based copper or (optical) fiber) [0052] data packets 50 are, after or while being received by the packet processing system, ingressed to the packet switching processor 20, and are, in order to be transmitted by the packet processing system 10, egressed by the traffic shaping processor 40, i.e. the processing chain of data packets 50 leads them to the packet switching processor 20 first and then to the traffic shaping processor 40. [0053] Hence, data packets 50 (comprising, as usual, a MAC information or MAC address (media access control address), an (or a plurality of) IP address indication(s) or information, a payload portion, etc.) are schematically represented, in Figure 1, at different points in the IP traffic packet processing chain according to the present invention: a first IP traffic packet 50 is schematically shown between packet switching processor 20 (or packet switching processor part 20 of the packet processing system 10), and the traffic shaping processor 40 (or traffic shaping processor part 40 of the packet processing system), wherein this first IP traffic packet 50 is schematically shown as having a queue identification information 51 appended. A second IP traffic packet 50 is schematically shown after the traffic shaping processor 40 (or traffic shaping processor part 40); the second IP traffic packet 50 has the queue identification information 51 removed as the queue identification information 51 primarily serves the purpose that the packet switching processor 20 is able to inform the traffic shaping processor 40 about the respective IP traffic packet 50, especially regarding its treatment and its processing and handling, especially with regard to its queue, etc. [0054] According to the present invention, the packet processing (of data packets 50) in the packet switching processor 20 is performed as known with a common packet processor, for example a Barefoot P4 or Broadcom NPL ASIC. After processing a packet (or a plurality of considered data packets), it is (or these are) forwarded to the traffic shaping processor 40, e.g. a second packet processor, which is exclusively responsible for queueing, or traffic shaping. The requirements to be solved by the first packet processor (or packet switching processor 20) can be fulfilled by many ASICs on the market (e.g. Barefoot Tofino, Broadcom Trident, ...), available in high volumes. In contrast, the second processor (traffic shaping processor 40) is only in charge of queueing/traffic shaping of pre-classified packets (i.e. data packets 50 having passed the packet switching processor 20, and having the queue identification information 51 appended), and thus has a lower functional complexity. Thus, the system provides the option to use FPGAs (in order to realize the traffic shaping processor 40) instead of using special-purpose ASICs.

[0055] According to the present invention, it is especially proposed to provide the packet processing system 10 with two hardware components, i.e. the packet switching processor 20 and the traffic shaping processor 40.

[0056] The packet (switching) processor 20 is able to append an information (especially the queue identification information 51) to the packet (i.e. to each of the data packets 50 traversing the packet processing system 10) which allows the subsequent shaping processor (traffic shaping processor 40) to determine a queue for the packet. Especially a queue ID 51 or queue identification information 51 is appended.

[0057] A straightforward option is to put the queue ID (or queue identification information 51) in front of the Ethernet header of the IP traffic packet 50. Alternatively, the queue ID information (or queue identification information 51) can be inserted at another position in the IP traffic packet 50, for example between the Ethernet and IP header (similar to a VLAN tag). The (traffic) shaping processor 40 is aware of the format of the inserted queueing information (e.g. the queue ID or queue identification information), removes the queue ID, and stores the IP traffic packet 50 in the specified queue of the traffic shaping processor 40. The queue ID (or queue identification information 51 can be either a simple consecutive number, or different parts of the ID have different meanings. An example thereof is shown in Figure 2.

The additional header (or queue identification information 51) within each of the data packets 50, independently from its position in the header stack, increases the average packet size whereas the payload size remains. In fact, this slightly reduces the useable bandwidth. This issue can be tackled, for example, by replacing the existing Ethernet headers with the queue ID header. The missing Ethernet header can be added after dequeuing the packets before sending them on the egress side of the whole system. This additional improvement works for all three placement methods. [0058] In Figure 2, an example of a queue identification information 51 is schematically shown. According to the present invention, the queue identification information 51 is appended to an IP traffic packet 50 by the packet switching processor 20, and, later on, used by the traffic shaping processor 40 to provide for a corresponding traffic shaping and scheduling. Different parts of the queue identification information 51 can be used to describe, for example, different shared links/resources in an access tree.

[0059] In the exemplary representation of the queue identification information 51 shown in Figure 2, the right-most three bits (“010”) exemplarily indicate a quality-of- service class (or a -bit QoS Class); the next six bits towards the left (“010101”) exemplarily indicate a n2-bit identifier; the next five bits towards the left (“10101”) exemplarily indicate a n3-bit identifier; the next five bits towards the left (“11011”) exemplarily indicate a n4-bit identifier; the next thirteen bits towards the left (“00000000000”) exemplarily indicate a further identifier or a 0-padding.

[0060] Reverting again to figure 1, both processors (i.e. the packet switching processor 20, and the traffic shaping processor 40) can have separate control plane interfaces for reconfiguration and flow rule installing. According to an exemplary embodiment according to the present invention, this is done over PCIe (Peripheral Component Interconnect Express) for all common ASICs. However, other technologies are available to implement the configuration interfaces, like JTAG (Joint Test Action Group), USB (universal seriral bus), I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface) or Ethernet.

[0061] The packet flow arrangement of the 2-chip queueing design of the packet processing system 10 can be used in different ways, however, the data packets 50 to be treated according to the concept of the present invention (i.e. passing the packet switching processor 20, then a queue identification information being appended, and then the traffic being shaped by the traffic shaping processor 40) are all traversing or are all passing through the packet processing system 10 in the same manner as described. It might be the case that - especially when implementing the concept according to the present invention in an aggregation network, where the downlink traffic (from the network to the clients or subscribers) typically needs shaping or needs to be shaped - data packets in the opposite direction, i.e. uplink data packets in an aggregation network, might traverse or pass through the packet processing system 10 in opposite direction (i.e. first pass through the traffic shaping processor 40, and then through the packet switching processor 20; however, in this case, such data packets are typically transparently transmitted through the packet processing system 10. For the purpose of implementing the present invention, the flow of the data packets 50 is always in the direction: Packet switching processor 20 towards traffic shaping processor 40, i.e. the packet goes only once through the packet processor and shaping processor; thus, the egress ports of the packet processing system 10 are connected to the traffic shaping processor 40 and the ingress ports are connected to the packet switching processor 20. In order to support bidirectional flows, a packet forwarding in the opposite direction must be implemented within the packet processing system 10, i.e. the IP traffic packet is received by the packet switching processor 20 and transmitted (with the queue identification information 51) to the traffic shaping processor 40. This design can utilize the chips up to the maximum bandwidth (because every packet is touched only once by each chip); in an alternative embodiment, it is possible to connect multiple shaping- processors (i.e. traffic shaping processor 40 units or modules) to one packet-processor (or packet switching processor 20) and vice versa. This also allows the use of special L1/L2 (layer 1 / layer 2) protocols such as Passive Optical Network (PON) technologies, such as GPON(Gigabit-capable Passive Optical Network), XGPON (Gigabit-capable PON), or XGSPON on the shaping-processor side (if supported by the shaping-chip) with standard packet-processors (which, e.g., only support Ethernet).

[0062] Figure 3 schematically illustrates a representation of further details of a traffic shaping processor 40 according to the present invention. The traffic shaping processor 40 comprises a first part 42 (or first module or first component), corresponding to or implementing a classifier or queue management algorithm. Inputs (or ingresses) (schematically denoted by reference sign A in Figure 3) to the traffic shaping processor 40 are provided to the first part 42. The traffic shaping processor 40 furthermore also comprises a second part 46 (or second module or second component), corresponding to or implementing a scheduling algorithm. Output (or egresses) (schematically denoted by reference sign S in Figure 3) from the traffic shaping processor 40 are provided by the second part 46. The traffic shaping processor 40 furthermore also comprises a queue part 44 or queue element. Each queue (five of which are schematically represented in Figure 3, but shown without an individual, respective reference sign) of the queue part 44 comprises an input side (schematically represented on the left hand side in Figure 3) and an output side (schematically represented on the right hand side in Figure 3). The processing of (payload) data, especially data packets and within the traffic shaping processor 40 can schematically be understood as follows: The first part 42 receives the incoming (or ingressing) data packets (collectively denoted by reference sign A), and distributes the incoming packets to the different queues of the queue part 44 as individual inputs a , a ₂ , az, a ₄ , as of the different queues of the queue part 44. The second part 46 takes individual data packets from the different queues of the queue part 44 as individual inputs Si, S2, S3, S4, S5 of the different queues of the queue part 44, and provides the resulting traffic (or egressing) as data packets (collectively denoted by reference sign S) to the egress of the traffic shaping processor 40 (and, as a consequence, to the egress of the packet processing system 10.

[0063] Hence, according to the present invention, it is proposed to separate the functionalities of a packet processor (or packet switching processor 20) on the one hand, and of the queueing behavior (or traffic shaping processor 40) on the other hand, especially in two separate chips or integrated circuits. Thereby, it is especially advantageously possible to realize a separation or disaggregation between the functionality of queue selection (provided for in the first chip or packet switching processor 20) and the functionality of queueing (provided for in the second chip or traffic shaping processor 40). Additionally - by means of using the queue identification information 51 - it is advantageously possible, according to the present invention, to realize an information encapsulation of queue affiliation in the packet bitstream, i.e. as part of the data packets that collectively correspond to the IP traffic to be processed and shaped by the packet processing system 10. According to the present invention, it is advantageously possible to provide for a usage of FPGAs, NPUs (network processing units) or other highly flexible programmable chips as shaping processor in order to increases the flexibility due to the possibility of implementing AQM-algorithms and (hierarchical) scheduling behavior. This advantageously provides the possibility to realize special queueing requirements (e.g. carrier access network queueing) with off-the-shelf hardware.