Title:
METHOD FOR MAKING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2005/045907
Kind Code:
A1
Abstract:
A method for making semiconductor integrated circuit devices, wherein a defective wafer that is out of spec can be detected in real time. A fault detection server (5) stores, in a device log data storing part (10), device log data outputted from a semiconductor making apparatus for processing semiconductor wafers. Thereafter, when a lot end signal receiving part (12) receives a lot end signal outputted from the semiconductor making apparatus, a fault data detecting part (15) refers to a fault detection condition setting file (13a) stored in a first detection condition storing part (13), and then determines, based on the content as referred to, whether there exist any fault data in the device log data stored in the device log data storing part (10). When detecting any fault, the fault data detecting part (15) outputs a detection result to an engineer PC or an operator terminal device.
Inventors:
TOKOROZUKI KAZUYUKI (JP)
NAKAJIMA TOSHIHIRO (JP)
MIYAMOTO YOSHIYUKI (JP)
FUKAYAMA YOSHIO (JP)
NAKAJIMA TOSHIHIRO (JP)
MIYAMOTO YOSHIYUKI (JP)
FUKAYAMA YOSHIO (JP)
Application Number:
PCT/JP2004/015835
Publication Date:
May 19, 2005
Filing Date:
October 26, 2004
Export Citation:
Assignee:
RENESAS TECH CORP (JP)
TOKOROZUKI KAZUYUKI (JP)
NAKAJIMA TOSHIHIRO (JP)
MIYAMOTO YOSHIYUKI (JP)
FUKAYAMA YOSHIO (JP)
TOKOROZUKI KAZUYUKI (JP)
NAKAJIMA TOSHIHIRO (JP)
MIYAMOTO YOSHIYUKI (JP)
FUKAYAMA YOSHIO (JP)
International Classes:
H01L21/02; H01L21/3065; H01L21/31; H01L21/00; (IPC1-7): H01L21/02
Foreign References:
| JPH10275753A | 1998-10-13 | |||
| JP2002149222A | 2002-05-24 | |||
| JPH09180976A | 1997-07-11 | |||
| JPH09129554A | 1997-05-16 |
Attorney, Agent or Firm:
Tsutsui, Yamato (3F Azeria Bldg., 1-1, Nishi-shinjuku 8-chome, Shinjuku-k, Tokyo 23, JP)
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