Title:
METHOD FOR MANUFACTURING INLET FOR IC TAG
Document Type and Number:
WIPO Patent Application WO/2007/141836
Kind Code:
A1
Abstract:
An inlet (100) for an IC tag is composed of an upper antenna (102) and a lower antenna
(103) for sandwiching a semiconductor chip (101) having an upper electrode (132)
and a lower electrode (133) from both the upper and lower sides, and a supporting
resin (104) for covering the semiconductor chip (101). The semiconductor chip
(101) is a super small chip having outer dimensions of 0.15 square mm or less and
a thickness of 10μm or less. In the manufacturing process of the inlet (100),
prior to sandwiching the semiconductor chip (101) between the upper antenna
(102) and the lower antenna (103), the entire surface of the semiconductor chip
(101) is coated with the supporting resin (104) and an effective volume is increased
so as to facilitate handling of the semiconductor chip (101).
Inventors:
USAMI MITSUO (JP)
Application Number:
PCT/JP2006/311132
Publication Date:
December 13, 2007
Filing Date:
June 02, 2006
Export Citation:
Assignee:
HITACHI LTD (JP)
USAMI MITSUO (JP)
USAMI MITSUO (JP)
International Classes:
G06K19/07; G06K19/077; H01L21/56; H01L21/683
Domestic Patent References:
| WO1999010935A1 | 1999-03-04 | |||
| WO2000036555A1 | 2000-06-22 |
Foreign References:
| JP2004127230A | 2004-04-22 | |||
| JP2005208787A | 2005-08-04 | |||
| JP2002269520A | 2002-09-20 | |||
| JP2000222540A | 2000-08-11 | |||
| JP2001217380A | 2001-08-10 |
Attorney, Agent or Firm:
TSUTSUI, Yamato (6th Floor Kokusai Chusei Kaikan, 14, Gobanch, Chiyoda-ku Tokyo, JP)
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