METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER - KWANSEI GAKUIN EDUCATIONAL FOUND

Title:

METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER

Document Type and Number:

WIPO Patent Application WO/2017/081862

Kind Code:

A1

Abstract:

In a first step, projections (42) are formed on the surface of an SiC substrate (40), and the SiC substrate (40) is etched. In a second step, at least a portion of an epitaxial layer (43a) is removed, the epitaxial layer (43a) including screw dislocations grown to a large size in a perpendicular (c-axis) direction by epitaxial growth of the projections (42) of the SiC substrate (40) by an MSE method. In a third step, the MSE method is again performed on the SiC substrate (40) for which the second step was performed, whereby epitaxial layers (43) not including screw dislocations are grown in a horizontal (a-axis) direction and thereby connected at a molecular level, and a single large-area single-crystal 4H-SiC semiconductor wafer (45) is generated on the entire Si face or C face of the SiC substrate (40).

Inventors:

KANEKO TADAAKI (JP)
KUTSUMA YASUNORI (JP)
ASHIDA KOJI (JP)

Application Number:

PCT/JP2016/004832

Publication Date:

May 18, 2017

Filing Date:

November 08, 2016

Export Citation:

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Assignee:

KWANSEI GAKUIN EDUCATIONAL FOUND (JP)

International Classes:

C30B29/36; C30B19/04; C30B19/12

Foreign References:

JP2010265126A	2010-11-25
JP2013043822A	2013-03-04

Other References: