A method of marking bits, a method of decoding bits, a bit marking device, a decoder, a receiver and a chip.

Technical Field

The present disclosure generally relates to the field of decoding technologies and, more specifically, to a method of marking bits to be decoded by a decoder, a method of decoding marked bits, a marking device, a decoder, a receiver comprising a decoder and a chip comprising a receiver.

Background

Forward Error Correction, FEC, as one of the techniques for error correction, is used in communication system, such as optical communication systems, to ensure reliable information transmission

Error detection and correction or error control techniques like FEC, are used in the area of telecommunication to enable reliable delivery of digital data over unreliable communication channels. In particular, FEC is a process of adding redundant data such as an error-correcting code, ECC, to a message so that the message can be recovered by a receiver even when a number of errors were introduced during the transmission over the communication channel.

To meet the ever increasing data demands in optical transport networks, OTNs, for example, optical line data rates are quickly shifting towards 400 Gbit/s and beyond. With the increase in data demands in optical transport networks, implementing soft-decision FEC, SD-FEC, decoders in the optical transport networks becomes increasingly challenging due to their high decoding complexity and internal data-flow. For this reason, considerable attention has lately been devoted to hard- decision FEC, HD-FEC, schemes whose decoding complexity and data-flow can be order of magnitudes less than SD-FEC.

In the context of HD-FEC, simple but powerful codes, such as product codes, PCs, and generalisation thereof, such as staircase codes, SCCs, offer at least at high coding rates a very good compromise between complexity and performance. This is due to the use of iterative algebraic decoding which is well known to be capacity-approaching at high rates in a binary-symmetric channel.

A product code constructed on a (n; k) component code is a set of square arrays of size n*n where any row and column of each array is a valid codeword in the component code. Typically, Bose-Chaudhuri-Hocquenghem (BCH) or Reed- Solomon codes are used as a component code. PCs based on BCH codes are typically decoded using iterative algebraic decoding methods such as iterative bounded distance decoding, BDD, which can lead to substantial coding gains.

However, a major performance limitation of BDD is caused by so- called decoding failures and miscorrections. A decoding failure is declared when a received vector of bits is not within a correction capability of a component code. A miscorrection instead occurs when the received vector is successfully decoded, but mapped into codeword different from the transmitted one.

A number of decoding strategies have been proposed to tackle both decoding failures and miscorrections, with an aim of improving the performance of BDD decoders whilst preserving a low-complexity algebraic structure. Most of these strategies somehow require the use of soft information from the channel and hence can be referred to as soft-aided HD, SAHD, schemes. However, the presently available SAHD algorithms can hardly guarantee high coding gains required by the increasing data rates of optical communication systems.

Therefore, there is a genuine need for a decoding scheme that can maintain low decoding complexity while improving decoding performance, especially in terms of net coding gains, of the decoding systems for HD-FEC codes, such as those used in optical communication systems.

Summary

In a first aspect of the present disclosure, there is presented a method of marking a sequence of bits to be decoded at a decoding iteration by a decoder, the sequence of bits being output bits from a previous decoding iteration of the decoder, the decoder employing hard decision forward-error correction decoding calculations, the method comprising the steps of:

receiving, from the previous decoding iteration, a plurality of reliability measures calculated respectively for the output bits, each of the reliability measures being based on a combination of a first indicator indicating whether a corresponding output bit is successfully decoded and a second indicator indicating a reliability of the corresponding output bit based on soft information available from a medium influencing the corresponding output bit;

marking the output bits with reference to the received reliability measures to generate a further sequence of bits to be decoded at the decoding iteration.

The present disclosure is based on the insight that marking a sequence of bits output from a previous decoding iteration or stage of a decoder, with reference to reliability measures respectively calculated for each of the output bits which take into consideration both potential decoding failures and possible miscorrections of the output bits, can effectively facilitate more reliable decoding of the sequence of output bits.

A reliability measure of an output bit is essentially a combination of two indicators or parameters, the first indicator takes one of a set of different values reflecting decoding correctness of the bit output from the previous decoding stage, while the second indicator indicates how reliable the output bit can be considered, by relying on soft information available from a medium that can influence the output bit.

A medium as used in the context of the present disclosure may refer to for example a communication channel in optical or wireless communication networks over which signals or data are transmitted, a storage medium having information stored thereon, for example related to magnetic, optical and solid state/flash based devices, or devices in security fields.

The reliability measures are then used to mark the output bits, to yield or generate a new or further sequence of marked bits, which will then be decoded by the decoder at the present decoding iteration or stage.

The reliability measures calculated according to the above method are simple to implement and will not jeopardize the simple-complexity of the HD decoding algorithm used to decode the bits marked with reference to the reliability measures.

For each decoding iteration, the reliability measures are updated based on a decision made by the decoder at a previous decoding iteration, thereby allowing the output bits to be decoded at the present iteration to be re-marked, facilitating the generation of a further decoding decision. The method of the present disclosure tackles both miscorrections and decoding failures, based on decoding decision from the previous decoding iteration and soft-information from for example the communication channel. It is demonstrated that decoding gains achieved by decoding the output bits marked using this new scheme are unprecedented for a decoder which still preserves its core HD decoding structure, such as a bounded distance decoder, BDD. As a result, it is possible to achieve decoding performance closer to soft decision, SD, decoding schemes, while still keeping decoding complexity and data-flow orders of magnitude below that of SD decoding schemes.

Following the above, it is noted that there might be at least two distinct forms of a medium. The first one is a medium for communicating data, e.g. a communication channel and the second one is a medium for storing data, for example a storage medium which stores data. In both situations it may become apparent that data that is communicated, or stored, gets corrupted which should then be corrected for.

In an embodiment of the present disclosure, the first indicator is an indication value selected from a predetermined set comprising values assigned respectively to correctly and incorrectly decoded bits, the indication value is further scaled with a scaling factor.

The decoder can, at each iteration, output or provide such as quantized a-posteriori information that indicates whether the output bits are correctly decoded. As an example, values -1 and +1 may be assigned for successfully decoded bits 0 and 1 , respectively, while a value of 0 will be assigned to the first indicator when a decoding failure occurs.

Such indicator information is simple and straightforward and requires little extra computation or storage resources. The introduction of this indicator therefore will not substantially increase decoding complexity of the core HD decoding algorithm of the decoder.

In an embodiment of the present disclosure, the scaling factor is a real-valued weight optimized for the decoding iteration using a bit error rate as a cost function to be minimized.

As an example, the scaling factor may be optimized based on an estimate for a bit error rate, BER, for a fixed signal-to-noise ratio. In practice, all scaling factors may be jointly optimized using Monte-Carlo estimates of the BER for the fixed as the optimization criterion.

Optimization of the scaling factor is performed numerically and different values are found for each decoding iteration. The optimal values of the scaling factors can also be optimally derived using a maximum-a-posteriori criterion.

In an embodiment of the present disclosure, the second indicator is a log-likelihood ratio, LLR, of an output bit.

The second indicator can be soft quantities or reliabilities extracted from for example the communication channel. One specific example is the LLR calculated as a bit reliability measure for the output bit.

In the conventional marking method, the marking is simply made with reference to absolute values of LLRs. In the present disclosure, the LLR is used together with the first indicator to arrive at a more sophisticated reliability measure, which will be used to mark the corresponding bit.

In an embodiment of the present disclosure, the step of marking comprising one of:

marking an output bit as reliable if the received reliability measure calculated for the output bit is greater than or equal to a marking threshold, and

marking an output bit as unreliable if the received reliability measure calculated for the output bit is smaller than the marking threshold.

By setting a marking threshold for the reliability measure, an output bit can be marked as either a (highly) reliable bit, HRB, if its reliability measure is greater than or equal to the marking threshold. Alternatively, if the reliability measure of an output bit is lower than the marking threshold, the output bit will be marked as a (highly) unreliable bit, HUB. These two classes are used to detect miscorrections.

The new marked bit will be passed to for example a decoding module of the decoder for further decoding.

In an embodiment of the present disclosure, the marking threshold is scaled with the scaling factor.

The marking threshold may be a fixed value. However, to further improve the decoding accuracy, the marking threshold can also be scaled with the scaling factor at each decoding iteration. A rationale behind this choice is minimising the probability of wrong miscorrection detection or non-detected miscorrection. The bit marking as a result is more reliable. In a second aspect of the present disclosure, there is presented a method of decoding a sequence of bits marked according to the method according to the first aspect of the present disclosure at a decoding iteration by a decoder, the sequence of bits being output bits from a previous decoding iteration of the decoder, the decoder employing hard decision forward-error correction decoding calculations, the method comprising the steps of

receiving the marked further sequence of bits;

decoding the further sequence of bits to generate a sequence of further output bits to be decoded at a next decoding iteration.

It can be contemplated by those skilled in the art that the marking of the bits output from a previous decoding iteration, taking into consideration both decoding failures the miscorrections there are potentially present, allows the received marked bits to be further decoded at the present iteration, giving a new or further sequence of output bits which are more reliable.

The decoding may be performed according to HD-FEC algorithms known to those skilled in the art, which means the bit marking may be used together with different HD decoding schemes to improve the decoding performance.

The decoding method provides a new attractive tradeoff between performance and decoding complexity in the context of high-speed HD-FEC schemes such as PCs and SCCs, for example.

In an embodiment of the present disclosure, the decoding method further comprises the step of calculating a further plurality of first indicators, each indicating whether a further output bit is successfully decoded, for a next decoding iteration.

When the output bits are remarked and decoded again at the present iteration, the decoder generates a further plurality of first indicators based on the decoding decision, which in turn will be used in a next decoding iteration for updating the reliability measures. This is beneficial as decoding at each iteration is performed using updated reliability measures.

In an embodiment of the present disclosure, the step of decoding comprising a step of flipping at least one of the further sequence of bits prior to the decoding step.

Bit flipping is used to facilitate the success of an additional decoding attempt. The decoder can never flip a bit from a previously successfully decoded codeword (zero-syndrome codeword); HRBs can never be flipped either. When either a failure occurs or a miscorrection is detected, a new decoding attempt is performed after bit flipping.

If after an additional decoding attempt a further failure or miscorrection is detected, the output bits are set equal to the decoder input and passed to a next decoding stage or iteration. This process is performed for a few iterations.

In a third aspect of the present disclosure, there is presented a marking device for marking a sequence of bits to be decoded at a decoding iteration by a decoder, the sequence of bits being output bits from a previous decoding iteration of the decoder, the decoder employing hard decision forward-error correction decoding calculations, the marking device comprising:

a receive module configured for receiving, from the previous decoding iteration, a plurality of reliability measures calculated respectively for the output bits, each of the reliability measure being based on a combination of a first indicator indicating whether a corresponding output bit is successfully decoded and a second indicator indicating a reliability of the corresponding output bit based on soft information available from a medium influencing the corresponding output bit; and a marking module configured for marking the output bits with reference to the received reliability measures to generate a further sequence of bits to be decoded at the decoding iteration.

The marking device may function as a marking module in a decoder to mark a sequence of bits to be decoded at the present iteration with reference to correctness and reliability of the bits output from the previous decoding iteration. Thus marked bits will be decoded by the decoder in a decoding attempt or iteration further to the previous decoding iteration, improving the overall decoding performance.

In a fourth aspect of the present disclosure, there is presented a decoder for decoding a sequence of bits marked by the marking device according to the third aspect of the present disclosure at a decoding iteration, the sequence of bits being output bits from a previous decoding iteration of the decoder, the decoder employing hard decision forward-error correction decoding calculations, the decoder comprising:

a receiving module configured for receiving the marked further sequence of bits; a decoding module configured for decoding the further sequence of bits to generate a sequence of further output bits to be decoded at a next decoding iteration.

In a fifth aspect of the present disclosure, there is presented a receiver at a receiving end of a communication channel in a communication system, the receiver comprising a decoder according to the fourth aspect of the present disclosure.

In a sixth aspect of the present disclosure, there is presented a chip comprising the receiver according to the fifth aspect of the present disclosure.

In a seventh aspect of the present disclosure, there is presented computer program product, comprising a computer readable storage medium storing instructions which, when executed on at least one processor, cause the at least one processor to carry out the method according to the first aspect of the present disclosure.

In an eight aspect of the present disclosure, there is presented computer program product, comprising a computer readable storage medium storing instructions which, when executed on at least one processor, cause the at least one processor to carry out the method according to the second aspect of the present disclosure.

The above mentioned and other features and advantages of the disclosure will be best understood from the following description referring to the attached drawings. In the drawings, like reference numerals denote identical parts or parts performing an identical or comparable function or operation.

Brief description of the drawings

Fig. 1 schematically illustrates a system model for a SABM scheme implemented in an exemplary receiver, in comparison with a standard HD decoding receiver.

Fig. 2 is a diagram schematically illustrating a workflow of a SABM algorithm for marking bits in comparison with a standard BDD algorithm without SABM.

Fig. 3 schematically illustrates how bit reliability measures are updated at each iteration for both row and column decoding. Fig. 4 schematically illustrates numerical results for a Product Codes, PCs, of rate ^ °· ⁷⁸ , respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR-ST algorithm.

Fig. 5 schematically illustrates numerical results for a Product Codes, PCs, of rate ^ ^{0 87} , respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR-ST algorithm.

Fig. 6 schematically illustrates a receiver implementing the algorithm for bit marking and decoding according to the present disclosure.

Detailed description

Embodiments contemplated by the present disclosure will now be described in more detail with reference to the accompanying drawings. The disclosed subject matter should not be construed as limited to only the embodiments set forth herein. Rather, the illustrated embodiments are provided by way of example to convey the scope of the subject matter to those skilled in the art.

The follow description of methods and devices of the present disclosure will be made with reference to exemplary embodiments relating to decoding of signals employing Product Codes, PCs and transmitted in an optical communication system, using iterative bounded distance decoding, BDD.

It will be appreciated by those skilled in the art that the technical solution of the present disclosure is suitable for other hard decision codes such as Hamming codes, Bose-Chaudhuri-Hocquenghem, BCH, codes, Reed-Solomon codes, and Staircase codes, SCCs and other iterative decoding algorithm.

It will also be appreciated by those skilled in the art that the technical solution of the present disclosure may also be applied to other technical areas, such as wireless communication system, security fields, storage systems or media and so on.

Iterative decoding is based on the idea of breaking up a decoding problem into a sequence of stages or iterations, such that each stage or iteration utilizes an output from previous decoding stages or iterations to formulate its own result.

Simple but powerful hard-decision FEC, HD-FEC, codes, such as product codes, PCs, and staircase codes, SCCs, are currently receiving consideration attention in their application to optical transport networks, OTNs. PC has been adopted, as an inner code, in the subclass 1.5 of ITU-T Recommendation G.975.1 , while SCC is part of the 400ZR Implementation Agreement, as an outer code, in the Optical Internetworking Forum. SCC is also recommended for 100G optical transport unit, OUT, order 4 for long-reach applications in the ITU-T Recommendation G.709.2/Y.1331.2.

Iterative BDD, as an iterative decoding algorithm, when applied to decode PCs, can lead to substantial coding gains. However, the error-correcting capability of BDD, that is, a number of incorrectly decoded bit f, is limited to where do is a the minimum Humming distance, MHD, of a component code. This limited error-correcting capability of BDD may lead decoding failures and miscorrections, which is considered as main performance limitation of BDD.

Specifically, BDD is used to decode, in Hamming space, a received bit sequence r for a component code C comprising codewords c. To correct up to t errors, the MHD do of C must satisfy d ₀ ³ 2t + 1. Thus, every codeword c in the code C can be associated to a sphere of radius t. Within such a sphere, no other codewords exist. If the received bit sequence rfalls inside one of these spheres, BDD will decode r to the corresponding codeword c. Otherwise, BDD will declare a failure.

Mathematically, for a given transmitted codeword c and a received bit sequence r, the BDD output ό is given by:

Where H(G, C) is the Hamming distance between r and c.

In practice, BDD is a syndrome-based decoder that uses syndromes to estimate the error pattern e. If the syndromes are all zeros, no errors are present. For the first two cases in equation (1), BDD will declare decoding success. In the second case, although BDD will still return an error pattern e, this case corresponds to a miscorrection. The third case is considered as decoding failure, and the received bit sequence r is output as the codeword.

One of the method proposed for solving the decoding failures and miscorrections with BBD is referred to as soft-aided bit-marking, SABM, scheme, which marks bits input to a decoding iteration using a bit reliability metric such as log- likelihood ratios, LLRs. Further decoding iterations are then performed based on marked bits, thereby improving the decoding performance, without compromising the complexity of HD-FEC schemes.

Figure 1 schematically illustrates a system model 10 of a receiver implementing a SABM scheme, in comparison with a standard HD decoding receiver.

The receiver may be an optical receiver or an optical transponder comprising a receiver module. In this case, in addition to functional blocks illustrated in Figure 1 , the receiver 10 may further comprise at least optical front end components, a digital signal processor, DSP, which provides digital signal input to a decoder, such as a FEC decoder in which a decoding algorithm as herein described is implemented.

The decoder may be implemented on, for example, a chip along with the DSP and other components of the receiver. It can be contemplated by those skilled in the art that the algorithm of the present disclosure may also be implementable in a non-optical system. The algorithm provides lower complexity, lower gate count in the chip, thereby lowering overall power consumption. Data flow within the chip is made more efficient by using the algorithm as disclosed herein, which contributes to lower power consumption.

It can be contemplated by those skilled in the art that the algorithm of the present disclosure may also be applied to other systems other than communication systems. In that case, the receiver will be a module or device comprising a decoder for decoding received bits.

It is assumed that information bits are encoded by an encoder and then mapped to symbols x _t taken from an equally-spaced M-ary PAM constellation S = {si, S2, . . ., SM}, with M= 2 ^m , m is a number of bits per symbol, where / is a discrete time index. The bit-to-symbol mapping may be for example a binary reflected Gray code. The received signal may be expressed as y _t = Jpxi + z _t , where z may be channel noise expressed for example as zero-mean unit-variance additive white Gaussian noise. For other application scenarios, z may be noise caused by a medium influencing the information bits.

The upper part of Figure 1 within a dashed box illustrates a standard HD receiver 1 1 comprising a decoder 1 12. In practice, a received signal y is input to an HD-based demapper 1 11 , which estimates code bits of the received signal. The estimated bits are then fed to the decoder 1 12 for decoding. With the receiver 10 implementing the SABM scheme, in addition to the HD-based demapper 1 1 1 , the received signal is also input to a bit reliability calculation module 1 13, which uses partial soft information from a medium influencing the received signal, such as a communication channel for transmitting the received signal, to determine reliabilities of bits of the received signal.

The soft information from the exemplary communication channel is typically represented using LLRs, which may be calculated as: h,k = {—l) ⁶ log

{*€{0,1} i

Where k = 1 ; ... . ;m, and where b donates bit negation. The set -^enumerates all the constellation points in S whose /cth bit c, * is b, that is, , , c _{i k} b}.

It is seen from Figure 1 that, apart from the HD-estimated bits, a sequence of bits marked by a bit marking module 1 14 will also be made available to the decoder 1 12. These marked bits can be marked as highly reliable bits, HRBs, highly unreliable bits, HUBs, or neither. The marking is made based on the absolute value of the LLRs _{i k} v.

Specifically, a bit with a LLR higher than or equal to a preset threshold will be marked as a HRB, while a bit with a LLR smaller than the preset threshold will be marked as HUB.

Figure 2 is a diagram 20 schematically illustrating a workflow of a SABM algorithm for marking bits in comparison with a standard BDD algorithm without SABM.

In the top part of Figure 2 above the dashed line 200, a standard BDD algorithm is shown. A received bit sequence r201 is successfully decoded 202 if there exists a codeword ό that differs by at most t positions from r, despite the possible existence of an error pattern e, where t is the error-correcting capability of the component code c. In this case, a decoded code word c' = t is output at 203. Otherwise, a failure is declared and the decoder simply outputs c' = r (not shown).

A successful BDD decoding does not always guarantee that the transmitted codeword c is correctly recovered. If more than t errors are introduced by a communication channel over which the codeword c is transmitted, and r is within t positions from a codeword c' ¹ c, the decoder will select c' as opposed to c, resulting in a so called miscorrection. Miscorrections often result in the decoder adding more errors than the ones introduced by the channel, thus leading to a deterioration of the BDD performance.

The SABM algorithm is shown in the lower part of Figure 2 below the dashed line 200. SABM tackles both decoding failures and miscorrections via a twofold action: miscorrection detection and bit flipping. This approach is enabled by the use of soft quantities or reliabilities extracted from the channel.

In SABM, LLRs are used as a bit reliability measure. By setting a threshold in the LLR magnitude, bits are marked as HRBs, when they fall above such a threshold. Alternatively, they are labelled as HUBs. Two rules are adopted to prevent a miscorrection: i) the BDD decoder can never flip a bit from a previously successfully decoded codeword; ii) HRBs can never be flipped. When either a failure occurs or a miscorrection is detected, a new decoding attempt is performed after bit flipping, as illustrated in Figure 2.

Specifically, with the SABM algorithm, after a decoding iteration that generates a decoded codeword ό with optionally an error pattern e, it is first determined at block 210 whether the decoding at the previous decoding stage is success. In the case of a positive result, it is further decided at block 220 whether a miscorrection is present. When no miscorrection occurs, at block 230, ό is output as the decoded codeword c' = ό.

Alternatively, when the decision block 210 gives a negative result, or when the decision block 220 gives a positive result, that is, in case of a decoding failure or a miscorrection, at block 240, bit flipping is performed to produce a new received bit sequence r’. Thereafter, a new decoding attempt, such as by BDD, is performed at block 250, to produce a new decoded codeword ό' with optionally an error pattern e’.

Thereafter, if it is determined at block 260 that the decoding is successful and at block 270 that no miscorrection is present, the decoded codeword ό' is output as the decoded codeword c' = ό' at step 280. When either decoding failure or a miscorrection occurs, the received sequence r is output at step 290.

Bit flipping is used to facilitate an additional decoding attempt. The LLRs of bits of the received sequence are ordered based on their magnitudes and the least reliable bit is flipped in the case of a failure. In the case of a detected miscorrection, the least dmn ^~ t ^{~ w} hi( ^e ) are flipped, where are the minimum Hamming distance of the component code and the error Hamming weight, respectively.

If after an additional decoding attempt a further failure or miscorrection is detected, the decoder output is set equal to the decoder input and passed to the next BDD decoding stage. This process is performed for a few iterations.

In the above described SABM algorithm, the bit marking occurs only once and is based on the channel LLRs. The same marking is then used over a certain number of iterations. This approach is, however, sub-optimal as the marking mask loses its validity after bits are updated at every iteration by the BDD decoder.

In view of this drawback, the present disclosure discloses a bit marking method that re-marks the output bits at each BDD iteration by defining a reliability measure for the outbound BDD decisions. This reliability measure combines the BDD decisions linearly with the channels LLRs.

Specifically, the BDD output can provide at each iteration (quantized) a-posteriori information by assigning values -1 , and +1 for successfully decoded bits 0 and 1 , respectively. When a failure occurs the output of the BDD will instead be identically set to 0.

Figure 3 schematically illustrates how bit reliabilities are updated at each iteration for both row and column decoding.

The specific example as illustrate in Figure 3 refers to one generic decoding iteration of a decoder applied to a PC. Each decoding iteration is illustrated to comprise two soft-aided bit-marking decoders. Each decoder deals with row decoding and column decoding, respectively.

Let u _j = {-1,0, +1} be the quantized a-posteriori information 31 provided by a row BDD decoder 32 for a bit in row / and column j. A scaled reliability ^{Yί ]} , SR 33, after row decoding at each iteration may be defined or calculated 34 as:

<Pi,j = w ^r ulj + k'j , i,j = 1,2, ... , n (3) where ^ are optimised real-valued weights and are for example the LLRs.

Block 34 may be implemented using operational gates of for example an Integrated Chip.

The SR 33 can be used to update a SABM marking stage 35. This approach is therefore referred as SABM-SR. A bit marking block takes as an input the SRs 33 from a previous (column) decoding stage or iteration, and yields a new set of marked bits Yu 36. The new marked bits 36 are then passed to a SABM row decoder

37 which produces a block of output bits ⁱ (not shown) and a corresponding block of a-posteriori information ^l 38. This information is then used to update again the reliabilities ^Rί · ⁷ according to equation (3). A marking update is then performed via the ^Rί · ⁷ for a SABM column decoder.

Differently from the prior art, here the reliability information at each iteration is used merely used to re-mark the bits at the input of the next BDD decoding iteration, and the BDD output ^D ' ⁷ is still used as the input of the next BDD decoder.

Additional data-flow required to update the reliability measure for each iteration is limited to a multiplication and an addition, which will cause negligible computation and storage burden to the currently available decoding algorithm.

It is seen from the above description with reference to Figure 3 that the scaled reliability of the present disclosure, which is updated for each decoding iteration including both row and column decoding, employs two parameters to respectively indicate success and reliability of bit sequence output from a previous r

decoding stage. That is, the first indicator ^Ul is a parameter generated for the bit sequence based on whether the bits are successfully decoded, and the second indicator reflects reliabilities of the bits.

A variant of the SABM-SR decoder described above may include adjustable marking thresholds to account for SRs scaling over multiple iterations. The rationale behind this choice is minimising the probability of wrong miscorrection detection or of not detecting a miscorrection. This variant of the SABM-SR decoding approach is referred to as SABM-SR-ST, where“ST” stands for“scaled threshold”.

In SABM-SR-ST, at each iteration the marking threshold is scaled by the same scaling factor experienced by the SRs ^{Yί ]} , rendering equation (3) in a new form as:

<Pi,i = ^{wr u} lj + ^wr h,j , i,j = 1-2,—, n (4)

Thus, as the number of decoding iterations increase, and the decoded bits become more reliable, the reliability threshold is also scaled accordingly.

It is seen that in SABM-SR-ST not only the extrinsic information from the decoder is scaled, but also the threshold that defines reliable and unreliable bits is. The threshold scaling factor is the same used for the reliabilities and, thus, the threshold is also updated at every decoding iteration.

The decoding process improved with the bit-marking method in accordance with the present disclosure is numerically assessed in an additive white Gaussian noise channel with binary antipodal modulation, 2PAM, and noise power spectral density .

Ten decoding iterations are run for all the implemented decoders. For SABM and SABM-SR decoders, a value of the reliability threshold was optimised and set to 5. The same value was chosen as initial threshold for the SABM-SR-ST decoder. For SABM, SABM-SR and SABM-SR-ST, a number of iterations where miscorrection detection (and bit flipping) is performed was optimised and set to 5 (out of 10) iterations. The SR weights and were numerically optimised for each iteration and the optimal weights were found to be [3.42, 3.87, 4.08, 4.27, 4.49] for the 5 marking iterations used for both SABM-SR and SABM-SR-ST decoders.

Figure 4 is a graph 40 that schematically illustrates numerical results for a set of PCs of rate ^ ^{0 78} (extended BCH (7,2, 1)), respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR- ST algorithm.

Figure 5 is a graph 50 that schematically illustrates numerical results for a PCs of rate ^ ^{0 87} (extended BCH (8,2, 1)), respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR- ST algorithm.

In Figure 4, a bit-error-rate, BER, vs a normalised signal-to-noise ratio

( E _b /N _{0 ou} tp _U t of the SABM-SR and SABM-SR-ST decoders are illustrated respectively as lines 41 and 42. Other decoding algorithms are also shown as a reference. These include a line 43 for iBDD, an ideal miscorrection-free iBDD, a line 44 for SABM, and a line 45 for turbo-product decoder, TPD, which adopts the so-called Chase-Pyndiah algorithm.

Similar lines are illustrated in Figure 5, for PC of rate ^ °· ⁸⁷ , that is, line 51 for SABM-SR, line 52 for SABM-SR-ST, line 53 for iBDD, line 54 for SABM, and line 55 for TPD.

It is shown that SABM-SR and SABM-SR-ST significantly outperform all other algorithms except TPD. However TPD can be considered a“fully-fledged” SD decoder and therefore of a much higher complexity than all other HD algorithms presented.

The present disclosure provides a simple and effective algorithm to improve the decoding of PCs as well as SCCs, without significantly increasing the decoding complexity, latency and decoder data-flow. Therefore, the present disclosure can be advantageously used many application involving HD decoders, in particular for example to relax the requirements on the optical transceivers or boost the transmission data rates in the 100G/400G or beyond OTNs.

Techniques used in this present disclosure are also suitable for other hard-decision codes that the optical communication community is interested in. For example, the method can be applied to concatenation coding schemes based on Hamming codes, BCH codes and Reed-Solomon codes for example. The algorithm could in principle boost the performance of all these codes.

On the other hand, hard-decision based codes are also used in wireless communications to ensure the reliable transmission of information. Therefore, techniques of this present disclosure may be used in wireless communications to prevent miscorrections and extend the error-correcting capability of BDD algorithms.

Moreover, SCCs have also attracted much attention from the security fields, e.g., using SCCs to construct threshold changeable secret sharing. It can be contemplated by those skilled in the art the present disclosure is also applicable to security field as it can improve the performance significantly.

Figure 6 schematically illustrates a receiver 60 implementing the algorithm for bit marking and decoding according to the present disclosure.

The receiver 60 may comprises, among others, a bit marking device 61 , and a decoder 62. Although illustrated as two separate devices, in practice the bit marking device 61 may be an integral part of the decoder 62.

The bit marking device 61 may comprise a bit reliability calculation module 63 configured for computing reliability measures for bits output from a previous decoding iteration based on information 64 received the previous decoding iteration, and sending the computed reliability measures to a bit marking module 65.

The bit marking module 65 is configured for marking the output bits based on the received reliability measures.

The marked bits are then fed to the decoder 62. The decoder 62 therefore may comprise a bit receiving module 66, and among others, a bit flipping module 67 and a decoding module 68. The received marked bits may be flipped by the bit flipping module 67 and then decoded at the decoding module 68.

Thereafter, decoded bits and indication information for calculation of reliability measures for the decoded bits are output 69 to a next stage or iteration.

It is noted that Figure 6 is for illustrative purpose only and shows only a decoding stage of the receiver.

The present disclosure is not limited to the examples as disclosed above, and can be modified and enhanced by those skilled in the art beyond the scope of the present disclosure as disclosed in the appended claims without having to apply inventive skills and for use in any data communication, data exchange and data processing environment, system or network.