The present invention relates in general to techniques for measuring the fluence of thermal neutrons and high energy hadrons (HEH).

It is known that thermal neutrons and hadrons (e.g. neutrons, protons, pions) with a kinetic energy higher than a few MeV may induce single event upsets (SEUs) in static random access memories (SRAMs) via indirect ionization. The hadronic fluence (d ) is proportional to the number of SEUs (N _SEU ) via the equation where a is the cross-section of the device per bit and N _bits is the memory size in bits. It is important to specify that SEU refers to the single physical event that generates the alteration of the logic state of one or more bits in memory. In fact, it is possible to observe SEU from single bit (single bit upset, SBU) or from multiple bit (multiple bit upset, MBU).

The cross-section depends on the device, the manufacturing technology, the supply voltage, the type and energy of the hadrons. Since SRAMs are not produced for use as fluence meters, this information is not provided by the manufacturers, but must be extracted with test campaigns in irradiation facilities (R. Harboe-Sorensen et al, “Design, testing and calibration of a ‘Reference SEU monitor’ system”, in Proc. RADECS, Sep. 2005, pp. B3-1-B3-7; R. Harboe-Sorensen et al, “From the reference seu monitor to the technology demonstration module onboard PROBA-II,” IEEE Trans. Nucl. Sci, vol. 55, no. 6, pp. 3082-3087, Dec. 2008). Some SRAM-based hadron fluence monitors are in use at CERN for the protection of the electronic systems of the Large Hadron Collider (S. Danzeca et al, IEEE Trans. On Nucl. Sci., vol. 61, no. 6, pp. 3458-3465, Dec. 2014). In this context, Cypress SRAMs irradiated with protons and neutrons have been characterized, showing a cross-section of the order of 10' ¹³ cm ² at energies higher than 50 MeV for protons and higher than 20 MeV for neutrons (Figure 1). Taking into account the memory size (8 Mb) and the cross-section, the sensitivity of the device [ (ffN _bits ) ~ ¹ ] turned out to be 1.25-10 ⁶ pp/cm ² (where pp indicates hadrons). Recently, hadron counters in proton therapy have been proposed for the characterization of the fast neutron field in the phantom (K. S. Ytre-Hauge et al., “First application of a novel SRAM-based neutron detector for proton therapy”, Radiation Measurements, Volume 122 , 2019, Pages 45-52).

Radiation-tolerant readout electronics is required to allow the reading of the response provided by the SRAMs; in this regard, solutions based on discrete components and application- specific integrated circuits (ASICs) have been implemented. Programmable devices, such as Field Programmable Gate Arrays (FPGAs) or central processing units (CPUs), have traditionally been excluded for such an application due to their sensitivity to radiation. Over the past few years, flash-based FPGAs for SRAM reading have been proposed at CERN (S. Danzeca. “The new version of the Radiation Monitor system for the electronics at the CERN electronic components radiation hardness assurance and sensors qualification.” pp. 37-38. Electronics. Universite Montpellier, 2015) and in proton therapy (K. S. Ytre-Hauge et al, Design and characterization of an SRAM-based neutron detector for particle therapy, NIMA, vol. 804, 2015, pp 64-71). However, such components may limit the lifetime of radiation monitors due to their relatively low total ionization dose (TID) tolerance (J. M. Armani et al, “TID Response of Various Field Programmable Gate Arrays and Memory Devices,” 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Moscow, 2015, pp. 1-4).

A limitation of prior art solutions is that they require separate components to detect SEUs and to read them, increasing power consumption, board complexity and board size. Furthermore, due to radiation tolerance requirements, the read-out logic is usually fixed and may not be reconfigured or updated once the system has been implemented.

One object of this invention is to provide a solution capable of at least partially resolving the prior art drawbacks.

In view of the aforementioned object, the object of the invention is a method for measuring hadron fluence with a Field Programmable Gate Array - FPGA, wherein the FPGA comprises:

- a Static Random Access Memory - SRAM - based configuration memory; - a programmable fabric comprising logic blocks, interconnections and input/output - I/O blocks;

- at least one access port to the SRAM-based configuration memory;

- a read-out logic realized in the programmable fabric, and whose functionality depends on data stored in the SRAM-based configuration memory, said read-out logic being capable of accessing the SRAM-based configuration memory through said at least one access port; wherein the SRAM-based configuration memory is susceptible of single event upsets induced by hadrons through indirect ionization, the SEU cross-section of the SRAM-based configuration memory having been preliminarily determined for at least one given particle in an energy range of interest and in a power supply voltage range of the FPGA; wherein the read-out logic is configured to: scan at least one subset of the SRAM-based configuration memory in order to verify whether the SRAM-based configuration memory remains in a predetermined logic state; and if the read-out logic detects that said at least one subset of the SRAM-based configuration memory differs from the predetermined state, i) provide, through the RO blocks, a time stamp of the detection of the difference, and therefore of the associated SEU, as well as for each detection an identification of each altered bit and of the relevant detected logic state, and ii) for each detection, restore the predetermined state in the SRAM-based configuration memory; wherein the read-out logic is protected by means of at least one radiation-hardening- by-design technique at architecture level, at logic place- and-route level or at configuration level, said at least one radiation-hardening-by-design technique comprising at least one technique selected from the group consisting of: triple modular redundancy, reliability- driven place-and-route constraints, redundant configuration access ports, background refresh of essential configuration bits, protection through cyclic redundancy check of at least part of the content of the SRAM-based configuration memory; wherein the method comprises: determining the hadron fluence as a function of said cross-section and of the count of SEUs in the SRAM -based configuration memory. Furthermore, the invention relates to a Field Programmable Gate Array - FPGA comprising:

- a Static Random Access Memory - SRAM - based configuration memory;

- a programmable fabric comprising logic blocks, interconnections and input/output - VO blocks;

- at least one access port to the SRAM-based configuration memory;

- a read-out logic realized in the programmable fabric, and whose functionality depends on data stored in the SRAM-based configuration memory, said read-out logic being capable of accessing the SRAM-based configuration memory through said at least one access port; wherein the SRAM-based configuration memory is susceptible of SEUs induced by hadrons through indirect ionization, the SEU cross-section of the SRAM-based configuration memory having been preliminarily determined for at least one given particle in an energy range of interest and at least in one power supply voltage range of the FPGA; wherein the read-out logic is configured to: scan at least one subset of the SRAM-based configuration memory in order to verify whether said at least one subset of the SRAM-based configuration memory remains in a predetermined logic state; and if the read-out logic detects that said at least one subset of the SRAM-based configuration memory differs from the predetermined state, i) provide, through the VO blocks, a time stamp of the detection of the difference, and therefore of the associated SEU, and for each detection an identification of each altered bit and of the relevant detected logic state, and ii) for each detection, restore the predetermined state in the SRAM-based configuration memory; wherein the read-out logic is protected by means of at least one radiation- hardening-by-design technique at architecture level, at logic place- and-route level or at configuration level, said at least one radiation-hardening-by-design technique comprising at least one technique selected from the group consisting of: triple modular redundancy, reliability-driven place- and-route constraints, redundant configuration access ports, background refresh of essential configuration bits, protection through cyclic redundancy check of at least part of the content of the SRAM-based configuration memory; wherein the read-out logic is configured to determine the hadron fluence as a function of said cross-section and of the count of SEUs in the SRAM-based configuration memory, or the FPGA is connectable to an external system configured to determine the hadron fluence as a function of said cross-section and of the count of SEUs in the SRAMbased configuration memory.

According to the invention, the FPGA implements both the sensing element (the SRAMbased configuration memory, otherwise called CRAM) and the read-out logic (the firmware in the fabric).

Due to the architecture of FPGAs, SEUs in the CRAM may corrupt programmed elements, including interconnections, thus preventing the read-out logic from functioning properly. The reading firmware in the fabric must be robust against SEUs and single event transients. To achieve this, it is possible to protect the read-out logic by means of radiation-hardening- by-design techniques at architecture level and by placing and interconnecting the logic, different techniques which are per se known. To convert the SEU count into fluence, the CRAM cross-section must be characterized as a function of energy and supply voltage by means of dedicated measurements at irradiation sites. Some neutron- specific characterization methods are shown in CN 108169660 A, which describes a method for determining the sensitivity of an FPGA to single particle effects induced by atmospheric neutrons, and in CN 105590653 A, which describes a test method for neutron-induced single-particle effects on a SRAM-based FPGA.

The features and advantages of the method and of the sensor according to the invention will become clearer from the following detailed description, made in reference to the accompanying drawings, provided purely for illustrative and non-limiting purposes, wherein:

- Fig. 1 shows the cross-sections per bit as a function of energy for the Cypress CY62157EV30 8Mb SRAM. In the left graph, proton cross-section data are fitted with a Weibull function and with a Weibull sum + power law (source: S. Danzeca et al, IEEE Trans. On Nucl. Sci., vol. 61, no. 6, pp. 3458-3465, Dec. 2014). In the right graph, neutron crosssection data are fitted with a Weibull function;

- Fig. 2 is the perspective representation of an FPGA hit by a hadron; - Fig. 3 conceptually shows the fabric, the CRAM and the access port to the CRAM of the FPGA of Fig. 1;

- Fig. 4 is a conceptual diagram of the fabric of the device of Fig. 2 (source: https://www.ni.com/it-it/innovations/white-papers/08/fpga-fu ndamentals.html);

- Fig. 5 illustrates examples of single event upsets in the CRAM that modify the logic and routing of signals in the fabric in an FPGA (source: https://api.semanticscholar.Org/CorpusID:55267460);

- Fig. 6 to 8 are diagrams representing different methodologies for minimizing single points of failure within the FPGA. In particular, Fig. 6 represents an example of modular redundancy applied at the fabric level (source: R. Giordano et al “Configuration Self-Repair in Xilinx FPGAs” IEEE Trans. On Nucl. Sci., Vol. 65, no.106, Oct. 2018), Fig. 7 represents an example of modular redundancy applied at the level of the printed circuit (source: Triple Module Redundancy Design Techniques for Virtex FPGAs, XAPP197 (v 1.0.1) July 6, 2006), and Fig. 8 represents the Xilinx(R) Isolation Design Flow methodology (source: Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq-7000 AP SoCs (ISE Tools), XAPP1086 (vl.3.1), Xilinx Inc., February 5, 2015).

With reference to Fig. 2 to 4, a Field Programmable Gate Array (FPGA) is shown, indicated as a whole with reference numeral 10. The FPGA 10 is of the type comprising a configuration memory based on Static Random Access Memory (SRAM), indicated with reference numeral 11 (hereinafter also indicated as CRAM). Fig. 2 symbolically represents a hadron, indicated with H, which impinges on the FPGA 10.

The FPGA 10 further comprises a programmable fabric 12, conventionally comprising logic blocks 13, interconnections 14 and input/output (RO) blocks 15.

The FPGA 10 further comprises at least one access gate, represented by the arrow 16 in Fig. 3 and configured to allow access to the SRAM -based configuration memory 11.

The FPGA 10 further comprises a read-out logic implemented in the programmable fabric 12; this read-out logic is able to access the SRAM-based configuration memory 11 through the access port 16. The SRAM-based configuration memory also acts as a sensing element to allow the determination of hadron fluence as a function of the number of SEUs in the CRAM 11. To convert the SEU count into fluence, the CRAM cross-section must be characterized as a function of energy and supply voltage by means of dedicated measurements at irradiation sites.

At the same time, the read-out logic is configured to detect and correct the altered bits in the CRAM 11 and in the fabric 12, implementing a self-correction function of the configuration and of the read-out logic itself. Information on the SEUs detected is transmitted to an external system (not shown) which determines the hadron fluence as a function of said cross-section and the number of SEUs in the CRAM 11.

More specifically, the read-out logic is configured to scan at least one subset of the CRAM 11 to verify if the CRAM 11 remains in a predetermined logic state.

If the read-out logic detects that this subset of the CRAM 11 differs from the pre-established state, it provides, through the I/O blocks 15, a time stamp of the detection of the difference, and therefore of the associated SEU, and for each detection an identification of each altered bit and of the relevant detected logic state, and for each detection, restores the predetermined state in the CRAM 11. An example of a configuration self-correction procedure is described in R. Giordano et al, “Configuration Self-Repair in Xilinx(R) FPGAs” IEEE Trans. On Nucl. Sci., Vol. 65, no.106, Oct. 2018.

The ways used to determine the expected state of the configuration memory 11, using only the FPGA and therefore without using external memories, are per se known. Some examples are given below:

1) verifying that the configuration not belonging to the read-out logic remains at its default value;

2) making the configuration memory bits redundant, as described in WO 2019/138282 Al, and performing a majority vote of their logic state;

3) compressing and storing the pre-established configuration in configuration bits related to unused resources (for example in block RAM available in the fabric).

As indicated above, the reading firmware in the fabric 12 must be robust against SEUs and single event transients. In fact, radiation induces SEUs that alter the logic and routing of the signals, as illustrated in the example of Fig. 5. Box a) represents an interconnection block 14 and a logic block 13 in their original logic state, while box b) represents the same blocks in which multiple bits have been altered by two SEU events (indicated by S 1 and S2) induced from radiation, changing the behavior of the system.

The read-out logic is therefore protected by techniques for hardening against radiation at the architectural level, such as triple modular redundancy, and at the logic placement and interconnection level, for example by using placement and interconnection constraints based on reliability (A. Aloisio et al, “Layout and Radiation Tolerance Issues in High-Speed Links” IEEE Trans. On Nucl. Sci., Vol. 62, no. 6, Dec. 2015; L. Sterpone et al, "A new reliability- oriented place and route algorithm for SRAM-based FPGAs" IEEE Trans. Comput. vol. 55 no. 6 pp. 732-744 Jun. 2006). Fig. 6 and 7 show examples of triple modular redundancy applied in the fabric 12 of the FPGA (Fig. 6) and on the printed circuit board hosting the FPGA (Fig. 7). Reference numeral 20 in Fig. 7 designates minority voting circuits, while reference numeral 21 designates pins of FPGA 10. The outputs of the FPGA are routed, at 22, to the printed circuit which houses such device. Fig. 8 represents the Xilinx(R) Isolation Design Flow methodology for limiting the propagation of faults between different modules built into the fabric of the same FPGA. In Fig. 8, reference numeral 31 designates a microprocessor, reference numeral 32 designates an isolated control function, reference numeral 33 designates an SEU sensing function, reference numerals 34 and 35 designate two isolated functions, reference numeral 36 designates a critical function for safety, and reference numeral 37 designates a redundant safety-critical function.

Other techniques consist, for example, in the adoption of redundant configuration access ports for device self-repair, or in the background refresh of the essential configuration bits (i.e. the bits which, if altered, potentially induce a malfunction of the particular circuit implemented in the fabric). It is also possible to protect at least part of the contents of the CRAM through a cyclic redundancy check (CN 104484238 A). According to an alternative embodiment, the read-out logic may also be totally self- contained, perform reconstruction of each SEU event with associated bad bit identification, store a SEU count, and even use the SEU count for on-chip fluence conversion via predefined look-up tables, without requiring any external fluence determination system.

According to one embodiment, it is possible to include boron in the fabrication of the FPGA to increase the sensitivity to thermal neutrons, and in principle it may be possible to add boron to the surface of the device after manufacturing. Through appropriate fault-injection measurements performed with pulsed lasers (e.g. V. Pouget et al., "Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection," 2008 14th IEEE International On-Line Testing Symposium, 2008, pp. 295-301, doi: 10.1109/IOLTS.2008.39) it is possible to associate the logical position of the bits in the CRAM with the physical position on the silicon die. This would allow the device to also be used to obtain some geometric information on the secondary particles, and therefore indirectly on the primary particle in order to create images of an object of interest irradiated with hadrons. A sensor for neutron, proton or pion imaging would then be made, depending on the primary particles used. More generally, for the purposes of the present invention it is meant that the expression “determining the hadron fluence” also includes the determination of a hadron fluence distribution as a function of the physical position on the die of the single cells of the SRAM-based configuration memory 11 of the FPGAs 10.

The solution described above allows the development of compact, reprogrammable, low power dissipation thermal neutron and high energy hadron (HEH) fluence sensors with integrated reading electronics with the following features:

- single device as sensing element and read-out electronics;

- reprogrammable read-out logic and interface configurable to back-end systems;

- compact board (area 30 cm ² );

- digital serial output (e.g. according to one of the following protocols JTAG, UART, SPI, I2C, CAN);

- low power (<1 W per sensor);

- reduced cost by using commercial off-the-shelf (COTS) components. As regards performance in terms of fluence sensitivity and radiation tolerance, the sensors are expected to be competitive with those of the prior art. The estimated figures, based on literature data from irradiation tests of Xilinx(R) 7-Series FPGAs, are as follows: - sensitivity of the order of 10 ⁶ pp/cm ² or higher (where pp indicates hadrons);

- radiation tolerance (TID > 1 kGy, 1 MeV equivalent neutron fluence > 10 ¹² n/cm ² , HEH fluence > 10 ¹² pp/cm ² ).