DIFFERENT REGIONS

GOVERNMENT RIGHTS

[0001] This invention was made with Government support under Agreement HR0011-11-9-0009 awarded by DARPA. The Government has certain rights in the invention.

FIELD OF THE INVENTION

[0002] Disclosed method and structural embodiments are directed to providing an integrated optoelectronic structure containing photonic devices having different optical properties in different regions of the structure.

BACKGROUND OF THE INVENTION

[0003] Optoelectronic integrated structures are fabricated to have photonic devices with different optical properties. Often such devices are fabricated using materials that either strongly interact with guiding light through one of an absorption/gain process for photon signal detection, or which allow guided light to propogate with minimal attenuation, such as in a waveguide. The conventional manner of achieving these different results is to use different elements and materials in differing spatial locations in the optoelectronic integrated circuit. In group III-V photonic integrated circuits, materials such as Ini _-X Ga _x Asj. _y P _y of varying mole fractions can be employed for this purpose. In silicon-based

optoelectronic integrated circuits other materials such as germanium or alloys thereof are utilized in combination with silicon. The integration of different materials in different regions of an optoelectronic integrated structure can add significantly to the cost and complexity of fabrication. [0004] It would be desirable to provide a low cost and easily integrated optoelectronic integrated structure in which the same optical material can, in some regions, provide an optical device having associated high signal attenuation, and other regions an associated low signal attenuation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a more complete understanding of the present embodiments, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

[0006] FIG. 1 is a cross-section of one example of a starting substrate for use in fabricating structural embodiments described herein;

[0007] FIG. 2 is a cross-section of the FIG. 1 structure after trench etching;

[0008] FIG. 3 is a cross-section of the FIG. 2 structure after a trench fill;

[0009] FIG. 4 is a cross-section of the FIG. 3 structure after a planarization of the trench fill and the formation of oxide and polysilicon materials;

[0010] FIG. 5 is a cross-section of the FIG. 4 structure after a patterned photoresist is applied;

[0011] FIG. 6 is a cross-section of the FIG. 5 structure after an etch operation;

[0012] FIG. 7 is a cross-section of the FIG. 6 structure after application of an amorphous silicon layer;

[0013] FIG. 8 is a cross-section of the FIG. 7 structure after a patterned photoresist is applied;

[0014] FIG. 9 is a cross-section of the FIG. 8 structure after an etch operation; [0015] FIG. 10 is a cross-section of the FIG. 9 structure after a further etch operation;

[0016] FIG. 11 is a cross-section of an example starting structure for another structural embodiment of the invention;

[0017] FIG. 12 is a cross-section of the FIG. 11 structure after application of a photoresist and illustrating an implant;

[0018] FIG. 13 is a cross-section of the FIG. 12 structure after removal of the photoresist;

[0019] FIG. 14 is a cross-section of the FIG. 13 structure after an etching operation;

[0020] FIG. 15 is a cross-section of the FIG. 14 or FIG. 10 structural after transistor implants;

[0021] FIG. 16 is a cross-section of FIG. 15 structure formation of an oxide material followed by formation of a nitride material;

[0022] FIG. 17 is a cross-section of the FIG. 16 structure after an etch operation;

[0023] FIG. 18 is a cross-section of the FIG. 17 structure after a silicide operation;

[0024] FIG. 19 is a cross-section of the FIG. 18 structure after a further etching operation; and,

[0025] FIG. 20 is a cross-section of the FIG. 19 structure after application of an oxide material. DETAILED DESCRIPTION OF THE INVENTION

[0026] Method and structural embodiments described herein provide a polysilicon material with different absorption losses in different regions of an optoelectronic integrated structure such that low loss waveguides and high absorption signal detector photonic devices can be formed in the different regions of the structure. Method and apparatus embodiments also provide an optoelectronic structure in which a polysilicon material is used to form transistor gates, a low loss waveguide, and a defect-state photodetector in different regions of the optoelectronic structure.

[0027] Generally, polysilicon, which is used for transistor gate formation in CMOS integrated circuits, has a high optical signal absorption. Method and structural embodiments described herein provide polysilicon material having lower optical absorption in regions intended for optical waveguide formation, while providing polysilicon having the inherent properties of a higher absorption in other regions of the optoelectronic structure for transistor gate formation and for defect-state photodetector formation.

[0028] Various method and structural embodiments of the invention will now be described in connection with the drawings. It should be understood that the specific method and structural embodiments described are examples and that modifications can be made without departing from the spirit or scope of the invention.

[0029] FIG. 1 illustrates a starting structure in the form of an example substrate 101. The substrate 101 can be formed of various materials on which optoelectronic integrated devices can be constructed, for example, substrate 101 can be a semiconductor substrate, for example, a silicon substrate.

[0030] FIG. 2 illustrates formation of various shallow trench regions 103 and deeper trench regions 105a and 105b within the substrate 101. Conventional

photolithographic techniques employing a pattern photoresist and etching can be used to form the trenches 103, 105a and 105b. [0031] Following the trench formation illustrated in FIG. 2, and as illustrated in FIG. 3, the trench areas 103, 105a, 105b are filled with an oxide material 107, for example, silicon dioxide. Shallow filled trench areas 103 will be used for electronic device isolation, while the deeper filled trenches 105a, 105b will be used for optically isolating overlying photonic devices from the substrate 101. Following this, the deposited oxide material 107 can be planarized down to the surface of the substrate 101 after which, as shown in Fig. 4, a further thin oxide 108, for example, silicon dioxide, can be grown or deposited on exposed surfaces of substrate 101 as a gate oxide for later transistor formation. Alternatively, the planarization of the oxide fill 107, as illustrated in FIG. 3 can be such that a thin layer of oxide 107 remains over the entire surface of the substrate 101 as a gate oxide 108.

[0032] In either case, as further illustrated in FIG. 4, after the formation of a thin gate oxide material 108, a polysilicon material 109 and an oxide material 1 1 1, e.g., silicon dioxide, are sequentially blanket deposited over the thin oxide material 108. The polysilicon material can be grown as a columnar polysilicon material 109. Following this, and as shown in FIG. 5, a pattern photoresist material 1 13 is formed having an opening 1 15 over the filled trench 105a. This opening is used, as shown in FIG. 6, as a mask for an etch through the oxide material 11 1 and columnar polysilicon material 109 to the level of the gate oxide material 108, forming opening 116.

[0033] As shown in FIG. 7, amorphous silicon 117 is formed over the FIG. 6 structure, including within the opening 116 shown in FIG. 6. The amorphous silicon 117 is formed under conditions that when it is later crystalized it will have different optical properties from the columnar polysilicon material 109. For example, silicon can be deposited under temperature of less than 550° C to provide the amorphous silicon material 117. As shown in FIG. 8, a photoresist 119 is patterned and located within opening 116 and over the filled trench 105a and amorphous silicon 117 within the opening 1 16 (FIG. 6). The photoresist 119 is used as a mask during an etching of the amorphous silicon 1 17 and oxide material 11 1, and to the level of columnar polysilicon material 109, resulting in the structure illustrated in FIG. 9. FIG. 9 now has the original columnar polysilicon material 109 and, separated therefrom, an amorphous silicon material 1 17 located over the deep trench 105a, which are both formed in the same plane at the same fabrication level. The FIG. 9 structure is subject to an annealing, e.g. greater than 600° C for about 30 minutes, process which crystallizes the amorphous silicon 1 17, into a polysilicon material 117a. The polysilicon material 117a started as an amorphous silicon layer, which when crystallized during annealing, has a different grain structure from the columnar polysilicon material 109. The different grain structure provides the polysilicon material 117a with a lower optical signal absorption characteristic compared with the higher optical signal absorption characteristic of the columnar polysilicon material 109.

[0034] FIG. 10 further illustrates a patterned etching of the columnar polysilicon material 109 to form, on the right side of FIG. 10, a gate 121 positioned between filled shallow trenches 103 for a transistor structure and on the left side, a polysilicon material element 122 which is over the filled deep trench 105b. The polysilicon material 1 17a, crystallized from amorphous silicon, can be used as a core of a low loss, low absorption waveguide structure. The columnar polysilicon material 109 has a higher absorption for photons and is suitable as a defect-state photodetector. Thus different polysilicon materials, having different optical properties, are formed in different regions of an optoelectronic structure at the same fabrication level.

[0035] FIG. 11 is a cross-section of a starting structure for other method and structural embodiments. It illustrates the substrate 101 , e.g. silicon substrate, the oxide filled shallow trenches 103 and the oxide filled deeper trench areas 105a and 105b. It also illustrates the gate oxide 108, and columnar polysilicon material 109 over the gate oxide. These materials can be formed in the same manner as described above with reference to FIGS. 1-4.

[0036] FIG. 12 illustrates the formation of a patterned photoresist 123 having opening 122 over the FIG. 11 structure, and over oxide filled trench area 105a, and a subsequent doping implant (shown by arrows) into the columnar polysilicon material 109 through the opening 122 of the photoresist material 123. The implant in FIG. 12 is a high energy dose of a dopant which penetrates the columnar polysilicon material 109 and disrupts its crystal structure converting it to amorphous silicon. For example, the dose can be 150 keV or higher with a dopant concentration of lE15/cm ^2' or higher. Although different dopants can be used, it is preferable to use silicon atoms. The dopant implant converts the implanted columnar polysilicon material 109 into amorphous silicon in the region below opening 122. This amorphous silicon region is illustrated in FIG. 13 as amorphous silicon region 109a. This region is then recrystallized back into a polysilicon material through a suitable high temperature anneal, e.g. 600° C for 30 minutes, or a rapid thermal anneal at 955° C for 20 minutes. The recrystallized polycrystalline material in region 109a possesses a different grain structure from that of columnar polysilicon material 109 giving it a lower photonic loss (lower attenuation) compared with the columnar polysilicon material 109.

[0037] FIG. 14 illustrates a subsequent etching of the polysilicon materials 109 and 109a to produce a transistor gate 121, a high photon absorption area 122 from columnar polysilicon material 109 for use as a phototector, and a lowerer loss low absorption polysilicon material 109a which can be used as a core for waveguide formation. Once again, the polysilicon materials 109, 109a formed in different regions of the optoelectronic integrated structure having different absorption properties. The lower 109a and higher 109 absorption polysilicon materials are fabricated in the same plane at a same fabrication level to provide a higher attenuation transistor gate 121 and a higher attenuation defect-state photodetector 122, and a lower loss lower attenuation waveguide core 109a.

[0038] FIG. 15 illustrates a starting structure for further processing which can either be the FIG. 14 structure or the FIG. 10 structure, as indicated by the polysilicon material 117 (or 109a) in FIG. 15. FIG. 15 further illustrates further processing by formation of source/drain regions 130 around gate 121 and an additional doped well 160. A threshold voltage (Vt) implant can also be provided for gate 121. The various implants for determining desired transistor characteristics are well known in the art.

[0039] FIG. 16 illustrates the subsequent formation of a thin oxide material 125, for example, silicon dioxide, and followed by a thicker nitride material 127, e.g., silicon nitride, as blanket depositions over the FIG. 15 structure. FIG. 17 illustrates the FIG. 16 structure after an etching to remove the nitride 127 and oxide 125 materials over the source/drain regions 130 and over the top of the transistor gate 121. This exposes upper areas of the gate 121 polysilicon material and substrate containing the source/drain regions 130 for a subsequent silicide operation. [0040] FIG. 18 illustrates the blanket deposition of a thin well known metal material 128 over the entire substrate for use in forming a silicide on exposed areas of polysilicon material of gate 121 and semiconductor substrate 101. The metal material can be, for example, cobalt, nickel, titanium, or other known silicide forming metals. Subsequently, a high temperature anneal converts the upper areas of the polysilicon in the gate 121 and silicon at the source/drain regions 130 into silicide areas 131, 132, shown in FIG. 19, providing highly conductive contacts. After the silicide areas 131, 132 are formed, the metal which remains on the nitride layer 127 and is unreacted is removed by a chemical etch, as further shown in FIG. 19.

[0041] FIG. 20 illustrates the selective etch and removal of the nitride 127 and optionally, the oxide 125, as shown, over the polysilicon material 122, which will be fabricated into a photodetector. It has been observed that removal of the nitride material 127 over the top surface of the polysilicon material 122 for use as a photodetector increases absorption and thus electrical signal output from the photodetector.

[0042] FIG. 21 illustrates the subsequent formation of an oxide material 135, for example, Si0 ₂ , or BPSG or PSG, over the entire structure and the subsequent formation of conductive vias 141 down to what is now a defect state photodetector 150 and to the source/drain and gate of transistor 152. The conductive vias can be formed of a doped polysilicon. At this stage, the polysilicon material 1 17 (or 109a) is now entirely surrounded by cladding material and is now a lower loss, lower absorption, waveguide 154, compared to the polysilicon material 121 which is now a gate for a transistor 152 and the polysilicon material 122 which is now a defect state photodetector 150.

[0043] The structure illustrated in FIG. 21 can now be further processed to complete an optoelectronic structure by forming interlayer dielectric (ILD) materials and associated metallization materials on and above oxide material 135 to interconnect the various photonic devices and circuit devices together, as well known in the art.

[0044] As evident from the foregoing, an optoelectronic structure is provided in which a polysilicon material has different attenuation and signal propogation characteristics in different regions. All fabricated polysilicon structures are also fabricated at the same physical level, i.e. at the transistor gate level to provide a lower loss, lower absorption waveguide 154 as well as a higher loss higher absorption defect state photodetector 150 and transistor gate 121.

[0045] While various embodiments of the invention have been described above, the invention is not confined to the specific disclosed method and structural embodiments as many modifications can be made without departing from the spirit or scope of the invention. Accordingly, the invention is not limited by the foregoing description but is only limited by the scope of the appended claims.